refactored getCopyFromParts and getCopyToParts, which are more general.
This effectively adds support for lowering illegal by-val vector call
arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37843 91177308-0d34-0410-b5e6-96231b3b80d8
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.
This fixes test/CodeGen/X86/negative-sin.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37842 91177308-0d34-0410-b5e6-96231b3b80d8
ordering and thus violated the strict weak ordering requirement of
priority_queue. Uncovered by _GLIBCXX_DEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37794 91177308-0d34-0410-b5e6-96231b3b80d8
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37781 91177308-0d34-0410-b5e6-96231b3b80d8
to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37755 91177308-0d34-0410-b5e6-96231b3b80d8
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37687 91177308-0d34-0410-b5e6-96231b3b80d8
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
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1. Consider all possible ifcvt cases at once. No longer restricted to bottom
up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37613 91177308-0d34-0410-b5e6-96231b3b80d8
