51 Commits

Author SHA1 Message Date
Tim Northover
27d489f3b2 ARM64: always use i64 for the RHS of shift operations
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.

Should fix PR19294.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 09:26:16 +00:00
Tim Northover
b642eb5dbc ARM64: don't generate __sincos_stret calls unless on MachO
This should fix PR19314.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 07:06:13 +00:00
Jim Grosbach
bc413d65a2 Make a few more range-based loops use explicit types.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 20:21:22 +00:00
Jim Grosbach
bc07242d9b Simplify resolveFrameIndex() signature.
Just pass a MachineInstr reference rather than an MBB iterator.
Creating a MachineInstr& is the first thing every implementation did
anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 19:28:18 +00:00
Jim Grosbach
b4e30b31e9 Make some range based loop types more explicit.
No functional change, but more readable code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 19:28:08 +00:00
Jim Grosbach
6408bdcacd [C++11,ARM64] Range based for and explicit 'override' in STP cleanup.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205446 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:59 +00:00
Jim Grosbach
252303f4ad [C++11,ARM64] Range based for loops in constant promotion.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:56 +00:00
Jim Grosbach
72ca0bfa7f [C++11,ARM64] Range based for loops in load/store pair optimizer.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205444 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:53 +00:00
Jim Grosbach
8c60cf143e [C++11,ARM64] Range based for loops in target lowering.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205443 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:51 +00:00
Jim Grosbach
cbc64ac10e [C++11,ARM64] Range based for loops in frame lowering.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205442 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:49 +00:00
Jim Grosbach
7e2d11d345 [C++11,ARM64] Range based for loops in pseudo expansion.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205441 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:46 +00:00
Jim Grosbach
4d59fd9cf0 [C++11,ARM64] Range based for loops for LOH
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:44 +00:00
Jim Grosbach
86ae767ea4 [C++11,ARM64] Range based for loops TLS cleanup.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205439 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:41 +00:00
Jim Grosbach
5e2ab67a19 [C++11,ARM64] Range based for loops in branch relaxation.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205438 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:39 +00:00
Jim Grosbach
68c150834b [C++11,ARM64] Range based for loops in address type promotion.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 18:00:36 +00:00
Quentin Colombet
a5084593ba [ARM64][CollectLOH] Remove the link to the radar from the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205435 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 16:40:49 +00:00
Tim Northover
6584d94610 ARM64: use GOT for weak symbols & PIC.
Weak symbols cannot use the small code model's usual ADRP sequences since the
instruction simply may not be able to encode a value of 0.

This redirects them to use the GOT, which hopefully linkers are able to cope
with even in the static relocation model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205426 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 14:39:11 +00:00
Tim Northover
671c92d886 ARM64: fix lowering of fp128 fptosi/fptoui
We were creating libcall nodes that returned an MVT::f128, when these
particular operations actually return an int of some stripe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 14:39:07 +00:00
Tim Northover
3844cadc9a ARM64: make sure first argument to INSERT_SUBVECTOR has right type.
Again, coalescing and other optimisations swiftly made the MachineInstrs
consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was
produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 14:38:58 +00:00
Tim Northover
87e824120d ARM64: convert fp16 narrowing ISel to pseudo-instruction
The previous attempt was fine with optimisations, but was actually rather
cavalier with its types. When compiled at -O0, it produced invalid COPY
MachineInstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205422 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 14:38:54 +00:00
Quentin Colombet
91b97ccd87 [ARM64][CollectLOH] Add some comments to explain how the LOHs
framework works (for the compiler part), since the design
document is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 01:02:28 +00:00
Aaron Ballman
5570517bec Fixing an MSVC warning about widening the result of a 32-bit shift implicitly. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 12:24:25 +00:00
Tim Northover
ed839120c4 ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205302 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 12:22:37 +00:00
Aaron Ballman
103683c4cb Fixing warnings in the MSVC build. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 12:22:20 +00:00
Tim Northover
acfb679618 ARM64: add patterns for more lane-wise ld1/st1 operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205294 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:37:09 +00:00
Tim Northover
233c567ea9 ARM64: fix bug in ld3r (1d) SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205293 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:37:03 +00:00
Manman Ren
c7e0a8178a Register allocator: set CSRFirstUseCost to 5 for ARM64.
A value of 5 means if we have a split or spill option that has a really
low cost (1 << 14 is the entry frequency), we will choose to spill
or split the really cold path before using a callee-saved register.

This gives us the performance benefit on SPECInt2k and is also conservative.

rdar://16162005


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 21:06:36 +00:00
Tim Northover
93b3fcae28 ARM64: add extra patterns for scalar shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:46 +00:00
Tim Northover
812a174ba4 ARM64: add extra scalar neg pattern & tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205208 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:42 +00:00
Tim Northover
b35ffdff16 ARM64: add patterns for scalar sqdmlal & sqdmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:38 +00:00
Tim Northover
9542846832 ARM64: add more patterns for commuted fmsub operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205206 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:34 +00:00
Tim Northover
4417e07e39 ARM64: shuffle patterns around for fmin/fmax & add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:30 +00:00
Tim Northover
576c3f709f ARM64: add more scalar patterns for usqadd & suqadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:26 +00:00
Tim Northover
13277a78bc ARM64: add more scalar patterns for reciprocal ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:22 +00:00
Tim Northover
8f93e159ed ARM64: add i64 scalar pattern for @llvm.arm64.abs
This will be used by the Clang front-end code for vabsd_s64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205202 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:17 +00:00
Tim Northover
2357a94977 ARM64: fix a couple of signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 10:21:36 +00:00
Alexey Samsonov
285606027b Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 07:59:33 +00:00
NAKAMURA Takumi
94821ac1eb ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205162 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 01:10:26 +00:00
Chandler Carruth
2530cd31f4 [ARM64] Fix materialization of an fp128 zero immediate. There currently
is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 00:02:10 +00:00
Chandler Carruth
1f408b1474 [ARM64] Fix a heap-use-after-free spotted by ASan.
StringRef::lower() returns a std::string. Better yet, we can now stop
thinking about what it returns and write 'auto'. It does the right
thing. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 09:08:07 +00:00
Tim Northover
bcf0c5fd73 ARM64: uncopy/paste helper function
It was doing functional but highly suspect operations on bools due to
the more limited shifting operands supported by memory instructions.

Should fix some MSVC warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 08:30:28 +00:00
Tim Northover
1eaafd7f38 ARM64: remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:35:48 +00:00
Tim Northover
c31891e350 ARM64: override all the things.
Actually, mostly only those in the top-level directory that already
had a "virtual" attached. But it's the thought that counts and it's
been a long day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205131 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:25:18 +00:00
Dmitri Gribenko
39d0be5ea2 Fix a few -Wdocumentation warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 19:40:32 +00:00
Benjamin Kramer
190e0a1d63 Detemplatize LOHDirective.
The ARM64 backend uses it only as a container to keep an MCLOHType and
Arguments around so give it its own little copy. The other functionality
isn't used and we had a crazy method specialization hack in place to
keep it working. Unfortunately that was incompatible with MSVC.

Also range-ify a couple of loops while at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205114 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 19:21:20 +00:00
Benjamin Kramer
17576b2e16 ARM64: Remove unused helper function, make others static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205112 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 18:00:49 +00:00
Tim Northover
e2c0b61c4f ARM64: format register strings without creating a local Twine.
It was causing horrible failures on some build-bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 15:35:57 +00:00
Tim Northover
9f36b66324 ARM64: use 64-bit constant even on 32-bit machines
Another existing bot failure so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 11:51:49 +00:00
Tim Northover
88ac45ffa7 ARM64: change format specifier to work on 32-bit targets
Existing tests were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205092 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 11:47:07 +00:00
Chandler Carruth
3734a337e9 [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.

Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 11:07:40 +00:00