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32 Commits

Author SHA1 Message Date
Tim Northover
f2f35a9ca3 AArch64/ARM64: print BFM instructions as BFI or BFXIL 
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207752 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-01 12:29:38 +00:00
Tim Northover
b1c1b8a78d ARM64: print fp immediates without using scientific notation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 16:13:34 +00:00
Tim Northover
44a2f5610d ARM64: print lsr instead of lsrv for variable shifts (etc) 
The canonical syntax for shifts by a variable amount does not end with 'v', but
that syntax should be supported as an alias (presumably for legacy reasons).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207649 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 13:37:07 +00:00
Tim Northover
ebde5a5e49 ARM64: use hex immediates for movz/movk instructions 
Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 11:19:40 +00:00
Tim Northover
87476b607c ARM64: hexify printing various immediate operands 
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 11:19:28 +00:00
Tim Northover
2a2cce79be ARM64: print canonical syntax for add/sub (imm) instructions. 
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-30 11:19:15 +00:00
Bradley Smith
8aa927abb5 [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207219 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-25 10:25:29 +00:00
Kevin Qin
78eedb15c9 [ARM64] Support crc predicate on ARM64. 
According to the specification, CRC is an optional extension of the
architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207214 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-25 09:25:42 +00:00
Kevin Qin
81ea345894 [ARM64] Enable feature predicates for NEON / FP / CRYPTO. 
AArch64 has feature predicates for NEON, FP and CRYPTO instructions.
This allows the compiler to generate code without using FP, NEON
or CRYPTO instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-23 06:22:48 +00:00
Bradley Smith
35fb92dadd [ARM64] Change SYS without a register to an alias to make disassembling more consistant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:58 +00:00
Bradley Smith
62293d1147 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:54 +00:00
Bradley Smith
c669ad900d [ARM64] Properly support both apple and standard syntax for FMOV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:49 +00:00
Bradley Smith
cb9ca905e3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:44 +00:00
Bradley Smith
42c672649c [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:36 +00:00
Bradley Smith
7face75878 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:22 +00:00
Bradley Smith
7b5940c0c0 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:18 +00:00
Bradley Smith
9a9fa81c1a [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:07 +00:00
Bradley Smith
5a09ce9ad1 [ARM64] Rename LR to the UAL-compliant 'X30'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:59 +00:00
Bradley Smith
37fe6627f6 [ARM64] Rename FP to the UAL-compliant 'X29'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:50 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:31 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:24 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
96e05ca4bf [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:42 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:36 +00:00
Bradley Smith
a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:11 +00:00
Bradley Smith
35b8c724c7 [ARM64] STRHro and STRBro were not being decoded at all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:49 +00:00
Bradley Smith
6307036c7c [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:45 +00:00
Bradley Smith
7ac29214ce [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:38 +00:00
Tim Northover
7b837d8c75 ARM64: initial backend import 
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-29 10:18:08 +00:00