Commit Graph

5 Commits

Author SHA1 Message Date
Benjamin Kramer
18de809b0c Force a CPU on test so it doesn't depend on microarchitectural scheduling decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-12 11:17:12 +00:00
Quentin Colombet
8c15b60ffe [DAGCombiner] Load slicing test case: attempt to really fix the buildbots (used sse4.2 instead of avx!).
<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 18:54:49 +00:00
Quentin Colombet
83f743a4d5 [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support.
This should fix the buildbots.

Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32

into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 18:29:42 +00:00
Quentin Colombet
4351741a3b [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails on ubuntu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 18:17:17 +00:00
Quentin Colombet
c34693f6ef [DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
 a = load i64* addr
 b = trunc i64 a to i32
 c = lshr i64 a, 32
 d = trunc i64 c to i32

into:
 b = load i32* addr1
 d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 18:01:14 +00:00