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125 Commits

Author SHA1 Message Date
Juergen Ributzka
2aa7106dd6 [ARM64] Never hoist the shift value of a shift instruction. 
There is no need to check if we want to hoist the immediate value of an
shift instruction. Simply return TCC_Free right away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206101 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-12 02:53:51 +00:00
Juergen Ributzka
940b67465d [ARM64] Fix the cost model for cheap large constants. 
Originally the cost model would give up for large constants and just return the
maximum cost. This is not what we want for constant hoisting, because some of
these constants are large in bitwidth, but are still cheap to materialize.

This commit fixes the cost model to either return TCC_Free if the cost cannot be
determined, or accurately calculate the cost even for large constants
(bitwidth > 128).

This fixes <rdar://problem/16591573>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206100 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-12 02:36:28 +00:00
Louis Gerbarg
5672630b7c Add ARM64 CLS patterns 
This patch adds patterns to generate the cls instruction ARM64. Includes tests
for 64 bit and 32 bit operands.

rdar://15611957

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206079 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 22:27:58 +00:00
Lang Hames
a02c32f31d Remove redundant symbolization support from MCDisassembler interface. 
MCDisassembler has an MCSymbolizer member that is meant to take care of
symbolizing during disassembly, but it also has several methods that enable the
disassembler to do symbolization internally (i.e. without an attached symbolizer
object). There is no need for this duplication, but ARM64 had been making use of
it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and
into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer
functionality from the MCDisassembler interface. Symbolization will now be
done exclusively through MCSymbolizers.

There should be no impact on disassembly for any platform, but this allows us to
tidy up the MCDisassembler interface and simplify the process of (and invariants
related to) disassembler setup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206063 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 20:07:58 +00:00
David Blaikie
77cf856e56 Implement depth_first and inverse_depth_first range factory functions. 
Also updated as many loops as I could find using df_begin/idf_begin -
strangely I found no uses of idf_begin. Is that just used out of tree?

Also a few places couldn't use df_begin because either they used the
member functions of the depth first iterators or had specific ordering
constraints (I added a comment in the latter case).

Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T>
where you needed iterator_range<idf_iterator<T>>)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206016 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 01:50:01 +00:00
Jim Grosbach
a117c712c7 [ARM64,C++11] Range'ify use-lists iterators in address type promotion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206013 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 01:13:10 +00:00
Jim Grosbach
62fc093cf2 [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206007 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 00:27:22 +00:00
Jim Grosbach
098f42dbc7 [ARM64,C++11]: More range-based loop simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206006 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 00:27:19 +00:00
Jim Grosbach
eb690d8491 [ARM64,C++11]: Range'ify loops in InstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205992 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 22:00:18 +00:00
Jim Grosbach
13772fb0a7 [ARM64,C++11]: Range'ify loops in the conditional-compare pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 21:49:24 +00:00
NAKAMURA Takumi
c137b5d6c4 ARM64/*/LLVMBuild.txt: Prune redundant deps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205963 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 12:46:13 +00:00
NAKAMURA Takumi
accaa640cf LLVMBuild.txt: Add missing dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205962 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 11:16:47 +00:00
NAKAMURA Takumi
6c5bb2e764 LLVMBuild.txt: Reformat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205961 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 11:16:17 +00:00
NAKAMURA Takumi
f2eed86ea5 Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid). 
FIXME: Could we use SmallString here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205950 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 03:05:59 +00:00
Saleem Abdulrasool
6c66c4d2eb ARM64: add an explicit cast to silence a silly warning 
GCC 4.8 complains with:
  warning: enumeral and non-enumeral type in conditional expression

Although this is silly and harmless in this case, add an explicit cast to
silence the warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205949 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 02:48:10 +00:00
Juergen Ributzka
d631cc4563 [ARM64] Fix immediate cost calculation for types larger than i64. 
The immediate cost calculation code was hitting an assertion in the included
test case, because APInt was still internally 128-bits. Truncating it to 64-bits
fixed the issue.

Fixes <rdar://problem/16572521>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205947 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-10 01:36:59 +00:00
Bob Wilson
5fa20923c5 Simple fix for build failures resulting from r205867. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205918 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 18:34:45 +00:00
Alp Toker
46d36be2eb Fix some doc and comment typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:47:27 +00:00
Bradley Smith
35fb92dadd [ARM64] Change SYS without a register to an alias to make disassembling more consistant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:58 +00:00
Bradley Smith
62293d1147 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:54 +00:00
Bradley Smith
c669ad900d [ARM64] Properly support both apple and standard syntax for FMOV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:49 +00:00
Bradley Smith
cb9ca905e3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:44 +00:00
Bradley Smith
19b573d9c9 [ARM64] Conditional branches must always print their condition code, even AL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205894 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:39 +00:00
Bradley Smith
42c672649c [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:36 +00:00
Bradley Smith
6a82fbc29f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:31 +00:00
Bradley Smith
ae30bea9d7 [ARM64] Add missing shifted register MVN alias to ORN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:26 +00:00
Bradley Smith
7face75878 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:22 +00:00
Bradley Smith
7b5940c0c0 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:18 +00:00
Bradley Smith
250f973d7f [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:12 +00:00
Bradley Smith
9a9fa81c1a [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:07 +00:00
Bradley Smith
86c067813c [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:03 +00:00
Bradley Smith
5a09ce9ad1 [ARM64] Rename LR to the UAL-compliant 'X30'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:59 +00:00
Bradley Smith
37fe6627f6 [ARM64] Rename FP to the UAL-compliant 'X29'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:50 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:31 +00:00
Bradley Smith
90c8a50b62 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:27 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:24 +00:00
Bradley Smith
47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:20 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
a8f8d292ca [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:11 +00:00
Bradley Smith
3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:06 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
dcb9231b8a [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:56 +00:00
Bradley Smith
84998a1fa9 [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:53 +00:00
Bradley Smith
4be472c874 [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:49 +00:00
Bradley Smith
b336e5d041 [ARM64] Remove ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:45 +00:00
Bradley Smith
96e05ca4bf [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:42 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:36 +00:00
Bradley Smith
01229fa891 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:27 +00:00