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22 Commits

Author SHA1 Message Date
Alp Toker
46d36be2eb Fix some doc and comment typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:47:27 +00:00
Bradley Smith
35fb92dadd [ARM64] Change SYS without a register to an alias to make disassembling more consistant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:58 +00:00
Bradley Smith
c669ad900d [ARM64] Properly support both apple and standard syntax for FMOV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:49 +00:00
Bradley Smith
6a82fbc29f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:31 +00:00
Bradley Smith
250f973d7f [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:12 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:31 +00:00
Bradley Smith
90c8a50b62 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:27 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:24 +00:00
Bradley Smith
47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:20 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:06 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:36 +00:00
Bradley Smith
4580af747e [ARM64] Add missing 1Q -> 1q vector kind alias 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:01 +00:00
Tim Northover
27d489f3b2 ARM64: always use i64 for the RHS of shift operations 
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.

Should fix PR19294.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205519 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 09:26:16 +00:00
Tim Northover
acfb679618 ARM64: add patterns for more lane-wise ld1/st1 operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205294 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-01 10:37:09 +00:00
Tim Northover
93b3fcae28 ARM64: add extra patterns for scalar shifts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 15:46:46 +00:00
Tim Northover
576c3f709f ARM64: add more scalar patterns for usqadd & suqadd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 15:46:26 +00:00
Tim Northover
8f93e159ed ARM64: add i64 scalar pattern for @llvm.arm64.abs 
This will be used by the Clang front-end code for vabsd_s64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205202 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 15:46:17 +00:00
Tim Northover
7b837d8c75 ARM64: initial backend import 
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-29 10:18:08 +00:00