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150 Commits

Author SHA1 Message Date
Owen Anderson
f6372aa1cc Move some more instruction creation methods from RegisterInfo into InstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-01 21:11:32 +00:00
Chris Lattner
264e6fec9f Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-01 01:05:34 +00:00
Chris Lattner
6410552250 Fix a problem where lib/Target/TargetInstrInfo.h would include and use 
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-01 01:03:04 +00:00
Owen Anderson
d10fd9791c Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the 
Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-31 06:32:00 +00:00
Chris Lattner
8aa797aa51 Add new shorter predicates for testing machine operands for various types: 
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-30 23:10:15 +00:00
Chris Lattner
f73823000e More cleanups for MachineOperand: 
- Eliminate the static "print" method for operands, moving it
    into MachineOperand::print.
  - Change various set* methods for register flags to take a bool
    for the value to set it to.  Remove unset* methods.
  - Group methods more logically by operand flavor in MachineOperand.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-30 21:56:09 +00:00
Chris Lattner
9a1ceaedc2 Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-30 20:49:49 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Owen Anderson
718cb665ca Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 04:06:50 +00:00
Dale Johannesen
13e8b51e3e Handle blocks with 2 unconditional branches in AnalyzeBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e Add a utility routine to check for unpredicated terminator instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:59:56 +00:00
Evan Cheng
126f17a176 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:44:17 +00:00
Evan Cheng
b5cdaa257e RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:05:48 +00:00
Evan Cheng
1e341729dd Relex assertions to account for additional implicit def / use operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 07:12:14 +00:00
Bill Wendling
f5da13367f What should be the last unnecessary <iostream>s in the library. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-07 22:21:48 +00:00
Evan Cheng
c0f64ffab9 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-27 23:37:22 +00:00
Chris Lattner
18258c6404 convert PPC::BCC to use the 'pred' operand instead of separate predicate 
value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-17 22:37:34 +00:00
Chris Lattner
289c2d5f45 rename PPC::COND_BRANCH to PPC::BCC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-17 22:14:47 +00:00
Chris Lattner
df4ed6350b start using PPC predicates more consistently. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-17 22:10:59 +00:00
Evan Cheng
6ce7dc2a97 Properly transfer kill / dead info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-15 20:58:11 +00:00
Evan Cheng
7ce4578353 Matches MachineInstr changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-13 23:36:35 +00:00
Chris Lattner
ef13982aa7 implement the BlockHasNoFallThrough hook 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:35:02 +00:00
Chris Lattner
7c4fe259f8 Implement support for branch reversal, fix a bug in branch analysis. 
This provides stuff like:

        cmpw cr0, r15, r29
        mr r14, r15
-       bge cr0, LBB3_111       ;bb656
-       b LBB3_90       ;bb501
+       blt cr0, LBB3_90        ;bb501
 LBB3_111:      ;bb656
        lwz r18, 68(r1)

which is particularly good for dispatch group formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 06:03:11 +00:00
Chris Lattner
879d09cf13 Simplify code, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 05:42:09 +00:00
Chris Lattner
54108068b7 implement support for inserting a cond branch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-21 05:36:13 +00:00
Chris Lattner
2dc7723474 add support for inserting an uncond branch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 18:06:55 +00:00
Chris Lattner
c50e2bcdf7 implement branch inspection/modification methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 21:21:17 +00:00
Chris Lattner
804e067042 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 00:48:23 +00:00
Chris Lattner
b410dc9977 Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-20 23:18:58 +00:00
Chris Lattner
b1d26f6665 Implement the getPointerRegClass method, which is required for the ptr_rc 
magic to work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-17 00:01:04 +00:00
Chris Lattner
e53f4a055f Move some methods out of MachineInstr into MachineOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 17:52:23 +00:00
Chris Lattner
9c09c9ec9d teach the ppc backend how to spill/reload vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:24:02 +00:00
Chris Lattner
335fd3c7c2 Add support for copying registers. still needed: spilling and reloading them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 20:03:58 +00:00
Chris Lattner
bbf1c72d51 implement TII::insertNoop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 23:49:55 +00:00
Nate Begeman
3b478b31e2 add 64b gpr store to the possible list of isStoreToStackSlot opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 21:07:50 +00:00
Chris Lattner
6524287c53 implement isStoreToStackSlot for PPC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 20:16:12 +00:00
Chris Lattner
4083960147 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 20:12:32 +00:00
Chris Lattner
14c09b81ea teach ppc backend these are copies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:50:36 +00:00
Nate Begeman
1d9d7427c4 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 00:28:58 +00:00
Nate Begeman
21e463b2bf More PPC32 -> PPC changes, as well as merging some classes that were 
redundant after the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-16 05:39:50 +00:00
Chris Lattner
16e71f2f70 Rename PPC32*.h to PPC*.h 
This completes the grand PPC file renaming


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:59:06 +00:00
Chris Lattner
2668959b88 Rename PowerPC*.h to PPC*.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:51:18 +00:00
Chris Lattner
4c7b43b43f Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:37:35 +00:00
Chris Lattner
eb5d47d99d Fix a CQ regression from my patch to split F32/F64 into seperate register 
classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-07 05:00:52 +00:00
Chris Lattner
919c032fa4 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. 
These are used to represent float and double values, and the two regclasses
contain the same physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 01:35:02 +00:00
Chris Lattner
043870dd85 Teach the code generator that rlwimi is commutable if the rotate amount 
is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-09 18:17:41 +00:00
Misha Brukman
b5f662fa03 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-21 23:30:14 +00:00
Nate Begeman
7af0248af4 Initial support for allocation condition registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 07:04:16 +00:00
Nate Begeman
cb90de37a7 Add ori reg, reg, 0 as a move instruction. This can be generated from 
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:26:12 +00:00
Misha Brukman
f2ccb77ee9 PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-17 04:55:41 +00:00