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1030 Commits

Author SHA1 Message Date
Colin LeMahieu
8e7359d3a7 [Hexagon] Adding doubleworld accumulating multiplies of halfwords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224267 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 20:17:46 +00:00
Colin LeMahieu
f8396b83c6 [Hexagon] Adding accumulating half word multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224266 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 20:10:28 +00:00
Colin LeMahieu
c3449d705b [Hexagon] Adding multiply with rnd/sat/rndsat 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224265 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 20:01:59 +00:00
Colin LeMahieu
e9e8f1fe77 [Hexagon] Adding encoding bits for halfword multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224261 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 19:22:07 +00:00
Reid Kleckner
2a59b5ed2d Move mips1 tests to test/MC/Disassembler/Mips/mips1 
This matches the pattern of the mips2 and 3 tests, as well as our normal
conventions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224254 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 17:56:02 +00:00
Vladimir Medic
77b6849e61 Add disassembler tests for mips3 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224253 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 16:19:34 +00:00
Vladimir Medic
7dfda5887e Add disassembler tests for mips2 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224252 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 15:58:20 +00:00
Vladimir Medic
6fe13a4f08 This is the first in a series of patches that add missing disassembler tests for mips platform. The patches are divided per version of mips CPU to keep the patches smaller and ease the review. There are no functional changes, code is changed only if new tests reveal a bug.This patch adds disassembler tests for mips1 CPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224251 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 15:22:33 +00:00
Colin LeMahieu
5271cab7c9 [Hexagon] Adding double word add/min/minu/max/maxu instructions and tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224153 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-12 21:29:25 +00:00
Colin LeMahieu
365cfbc3f0 [Hexagon] Adding J class call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224150 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-12 21:12:27 +00:00
Colin LeMahieu
015408c6b1 [Hexagon] Adding encoding information for sign extend word instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-11 16:43:06 +00:00
Colin LeMahieu
b1fac191b2 [Hexagon] Adding combine ri/ir instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223971 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-10 22:23:07 +00:00
Colin LeMahieu
f6492bc6b2 [Hexagon] Adding encodings for JR class instructions. Updating complier usages. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223967 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-10 21:24:10 +00:00
Colin LeMahieu
9f3b3bca89 [Hexagon] Adding JR class predicated call reg instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223933 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-10 18:24:16 +00:00
Colin LeMahieu
11fa90091b [Hexagon] Fixing broken tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223823 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-09 20:36:53 +00:00
Colin LeMahieu
20856353b8 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223821 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-09 20:23:30 +00:00
Colin LeMahieu
260731d108 [Hexagon] Adding word combine dot-new form and replacing old combine opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223815 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-09 19:23:45 +00:00
Colin LeMahieu
60d733acc5 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223800 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-09 18:16:49 +00:00
Colin LeMahieu
73ed2dcdac [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223710 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 23:07:59 +00:00
Colin LeMahieu
7ec769c971 [Hexagon] Fixing broken test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223704 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 22:29:06 +00:00
Colin LeMahieu
27fbb34173 [Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223702 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 22:19:14 +00:00
Colin LeMahieu
9804956609 [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223701 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 21:56:47 +00:00
Colin LeMahieu
7b9be18636 [Hexagon] Adding xtype parity, min, minu, max, maxu instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223693 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 21:19:18 +00:00
Colin LeMahieu
a321bd4f19 [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223692 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 20:33:01 +00:00
Colin LeMahieu
4772502317 [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223680 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 18:33:49 +00:00
Colin LeMahieu
cf2daa3671 [Hexagon] Adding combine reg, reg with predicated forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 17:33:06 +00:00
Colin LeMahieu
5c7adadf6d [Hexagon] Adding packhl instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 17:01:18 +00:00
Colin LeMahieu
ec51bc6f3a [Hexagon] Adding sub/and/or reg, imm forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 21:38:29 +00:00
Colin LeMahieu
5db47f1376 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223515 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 21:09:27 +00:00
Colin LeMahieu
4fda99f866 [Hexagon] Adding tfrih/l instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223506 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 20:07:19 +00:00
Colin LeMahieu
189606dbfe [Hexagon] Adding add reg, imm form with encoding bits and test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223504 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 19:51:23 +00:00
Colin LeMahieu
78ec9010c5 [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223494 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 18:24:06 +00:00
Colin LeMahieu
0785bdf107 [Hexagon] Adding combine reg-reg forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223485 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 17:38:36 +00:00
Colin LeMahieu
4c58675d35 [Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223482 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-05 17:27:39 +00:00
Colin LeMahieu
0af45bd715 [Hexagon] Adding lit exception if Hexagon isn't built. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223335 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-04 04:28:38 +00:00
Colin LeMahieu
152ac18e80 [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223334 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-04 03:41:21 +00:00
Asiri Rathnayake
dc05f3a64b Add support for ARM modified-immediate assembly syntax. 
Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit
integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly
syntax support in LLVM allows the decoded (32-bit) immediate to be specified
as a single immediate operand for such instructions:

mov r0, #4278190080

The ARMARM defines an extended assembly syntax allowing the encoding to be made
more explicit, as in:

mov r0, #255, #8 ; (same 32-bit value as above)

The behaviour of the two instructions can be different w.r.t flags, which is
documented under "Modified immediate constants" in ARMARM. This patch enables
support for this extended syntax at the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223113 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-02 10:53:20 +00:00
Vladimir Medic
462763dc0b The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223006 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 11:12:04 +00:00
Charlie Turner
94df8b11bc Add post-decode checking of HVC instruction. 
Add checkDecodedInstruction for post-decode checking of instructions, to catch
the corner cases like HVC that don't fit into the general pattern. Needed to
check for an invalid condition field in instruction encoding despite HVC not
taking a predicate.

Patch by Matthew Wahab.

Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222992 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 08:50:27 +00:00
Charlie Turner
eed2e8bf98 Add Thumb HVC and ERET virtualisation extension instructions. 
Patch by Matthew Wahab.

Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222990 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 08:39:19 +00:00
Charlie Turner
42563acbd4 Add ARM ERET and HVC virtualisation extension instructions. 
Patch by Matthew Wahab.

Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-01 08:33:28 +00:00
Hal Finkel
186abcb853 [PowerPC] Add asm support for cache-inhibited ld/st instructions 
Add assembler support for the fixed-point cache-inhibited load/store
instructions. These are hypervisor-level only, so don't get too excited ;)

Fixes PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222976 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-30 10:15:56 +00:00
Jozef Kolek
b087448a5f [mips][microMIPS] Implement NOP aliases 
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222953 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-29 13:29:24 +00:00
Charlie Turner
3a8b98c984 Fix wrong encoding of MRSBanked. 
Patch by Matthew Wahab.

Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222920 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-28 15:01:06 +00:00
Daniel Sanders
68de93c3b4 [mips] Add synci instruction. 
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 17:28:10 +00:00
Jozef Kolek
2b8e58cc82 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 
Differential Revision: http://reviews.llvm.org/D6419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 14:41:44 +00:00
Jozef Kolek
832e2301cd [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 
Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 18:56:38 +00:00
Hal Finkel
b932ed3c3d [PowerPC] Add the 'attn' instruction 
The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222712 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-25 00:30:11 +00:00
Jozef Kolek
18700de8fc [mips][microMIPS] Implement disassembler support for 16-bit instructions 
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 13:29:59 +00:00
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 16:44:02 +00:00