69df72367f
Fix 80-column violations and whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03 21:46:10 +00:00
9e56fb12c5
Changed llvm-mc arm target to give an error if .syntax divided is used. Since
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only .syntax unified is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27 23:22:36 +00:00
bf7553210a
Introduce virtual ParseRegister method in TargetAsmParser.
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Create override of this method in X86/ARM/MBlaze.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27 17:14:22 +00:00
e47f3751d7
Fix the encoding and parsing of clrex instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 19:18:32 +00:00
8dd37f7b7d
Add cdp/cdp2 instructions for thumb/thumb2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:32:09 +00:00
b32f7a5f4b
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
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in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:06:58 +00:00
fa5bd27fbe
Add mcr* and mr*c support to thumb targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 16:35:57 +00:00
892fc6d7b6
Fix the encoding of t2ISB by using the right class and also parse it correctly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 21:17:09 +00:00
fdcee77887
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 20:55:11 +00:00
4b462672d2
McARM: Use accessors where appropriate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:55:27 +00:00
6ec56204f3
McARM: Fill in ASMOperand::dump() for memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:55:21 +00:00
2637dc9a25
McARM: Make ARMOperand use a union where appropriate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:55:15 +00:00
05d8b71424
McARM: Unify ParseMemory() successfull return.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123740 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:34:24 +00:00
0571093f4c
McARM: Early exit on failure (NEFC).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:34:17 +00:00
d3df5f32c0
McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic.
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Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:34:11 +00:00
023835d51b
McARM: Add a variety of asserts on the sanity of memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123737 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:34:05 +00:00
81f453c4b9
McARM: Use a consistent marker for not-set OffsetRegNum.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 05:33:57 +00:00
0c9f250d54
Recognize alternative register names like ip -> r12.
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Fixes <rdar://problem/8857982>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 22:50:36 +00:00
e4e5e2aae7
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
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the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.
With this, we can properly pretty-print and encode assembly like:
mrc p15, #0 , r3, c13, c0, #3
Fixes <rdar://problem/8857858>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 21:46:02 +00:00
67b212e03b
Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and
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directional local labels like 1f and 2b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123393 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 20:32:36 +00:00
7597212abc
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
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in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 07:58:56 +00:00
fef9ff4922
Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or
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.code 32 if the TargetMachine's isThumb() boolean does not match. The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 01:07:01 +00:00
8a8696db6b
Change call to Error() to assert()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13 00:27:00 +00:00
7caebff83d
Sort the register list based on the *actual* register numbers rather than the
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enum values we give to them. <rdar://problem/8823730>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-12 21:20:59 +00:00
9081b4b4cf
Workaround for bug 8721.
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.s Test added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 23:53:41 +00:00
b72d2a92b7
Clean up ARM subtarget code by using Triple ADT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 21:46:47 +00:00
eb9f3f91c0
McARM: Fill in GetMnemonicAcceptInfo().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 19:06:29 +00:00
3771dd041f
McARM: Sketch some logic for determining when to add carry set and predication code operands based on the "canonical mnemonic".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123239 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 15:59:53 +00:00
352e148cbe
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
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carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11 15:59:50 +00:00
8ab1112bdc
McARM: Flush out hard coded known non-predicated mnemonic list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 21:01:03 +00:00
6a5c22ed89
MC/ARM/AsmParser: Minor nitty fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 15:26:21 +00:00
badbd2fde9
MC/ARM/AsmParser: Split out SplitMnemonicAndCC().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 12:24:52 +00:00
2c502f915f
Formatting changes. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122789 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-03 23:59:05 +00:00
f12eee75d1
Use a StringSwitch<> instead of a manually constructed string matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122530 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 00:03:39 +00:00
940c8e5494
Recognize a few more documented register name aliases for ARM in the asm lexer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 23:19:54 +00:00
9584bd83e6
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 23:26:02 +00:00
f4caf69720
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
44a9e8f869
Fix the leak from r121401 of the Operands erased in the list but not deleted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 01:41:56 +00:00
193c3acbe5
Add support for parsing ARM arithmetic instructions that update or don't update
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the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:19:43 +00:00
6aa4943599
Add parens to pacify gcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 15:50:35 +00:00
04f74942f2
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
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the instruction is predicated, reg0 otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:30:57 +00:00
d67641b6f8
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
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not an immediate. It stores either ARM::CPSR or reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:21:12 +00:00
1fd374e9c1
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
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t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 22:57:21 +00:00
ef4a68badb
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 07:44:32 +00:00
00a257af5b
Add a few missing initializers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:41:10 +00:00
03f44a04e6
Nuke trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 23:18:01 +00:00
9717fa9f29
The "trap" instruction is one of this which doesn't have a condition code. Hack
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the code to not add a "condition code" if it's trap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 10:56:05 +00:00
cb21d1c9fd
Use array_pod_sort because the list is contiguous.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 00:38:19 +00:00
50d0f58944
Add support for parsing the writeback ("!") token.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:43:05 +00:00
24d22d2764
Don't allocate the SmallVector of Registers. It gets messy figuring out who
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should delete what when the object gets copied around. It's also making valgrind
upset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 21:50:54 +00:00
