4 Commits

Author	SHA1	Message	Date
Jakob Stoklund Olesen	5047d76575	Pseudo CMOV instructions don't clobber EFLAGS. ... The explanation about a 0 argument being materialized as xor is no longer valid. Rematerialization will check if EFLAGS is live before clobbering it. The code produced by X86TargetLowering::EmitLoweredSelect does not clobber EFLAGS. This causes one less testb instruction to be generated in the cmov.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen	b0e47cdf3d	Fix register-dependent X86 tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128867 91177308-0d34-0410-b5e6-96231b3b80d8	2011-04-05 00:32:44 +00:00
Dan Gohman	bc7588eb68	Add another variant of this test which found a place where ... CodeGen's ComputeMaskedBits was being over-conservative when computing bits for an ADD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101963 91177308-0d34-0410-b5e6-96231b3b80d8	2010-04-21 00:19:28 +00:00
Chris Lattner	d6139425f5	teach the x86 address matching stuff to handle ... (shl (or x,c), 3) the same as (shl (add x, c), 3) when x doesn't have any bits from c set. This finishes off PR1135. Before we compiled the block to: to: LBB0_3: ## %bb cmpb $4, %dl sete %dl addb %dl, %cl movb %cl, %dl shlb $2, %dl addb %r8b, %dl shlb $2, %dl movzbl %dl, %edx movl %esi, (%rdi,%rdx,4) leaq 2(%rdx), %r9 movl %esi, (%rdi,%r9,4) leaq 1(%rdx), %r9 movl %esi, (%rdi,%r9,4) addq $3, %rdx movl %esi, (%rdi,%rdx,4) incb %r8b decb %al movb %r8b, %dl jne LBB0_1 Now we produce: LBB0_3: ## %bb cmpb $4, %dl sete %dl addb %dl, %cl movb %cl, %dl shlb $2, %dl addb %r8b, %dl shlb $2, %dl movzbl %dl, %edx movl %esi, (%rdi,%rdx,4) movl %esi, 8(%rdi,%rdx,4) movl %esi, 4(%rdi,%rdx,4) movl %esi, 12(%rdi,%rdx,4) incb %r8b decb %al movb %r8b, %dl jne LBB0_1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8	2010-04-20 23:18:40 +00:00