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20 Commits

Author SHA1 Message Date
Hao Liu
2825b8f0ea [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR32 registers in copyPhysReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201061 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 03:16:22 +00:00
Chad Rosier
dafea158a7 [AArch64] Custom lower concat_vector patterns with v4i16, v4i32, v8i8, v8i16, v16i8 types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200491 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-30 21:46:54 +00:00
Kevin Qin
8ab549b856 [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR. 
Replace r199791.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200180 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-27 02:53:54 +00:00
Kevin Qin
73840852cf Revert r199791. 
It's old version which has some bugs. I'll commit lattest patch soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200179 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-27 02:53:41 +00:00
Kevin Qin
97581ccb89 [AArch64 NEON] Add patterns for concat_vector on v2i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200111 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-26 02:46:15 +00:00
Kevin Qin
b1fadec968 [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199978 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 07:53:04 +00:00
Hao Liu
fa6e5cb511 [AArch64]Add CHECK for two test cases testing scalar_to_vector committed in r199461. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 02:09:30 +00:00
Kevin Qin
0af7a7db53 [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199791 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 06:11:03 +00:00
Hao Liu
555f57f67b [AArch64]Fix the problem can't select concat_vectors of two v1i32 types. 
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-17 05:44:46 +00:00
Kevin Qin
63735e79ff [AArch64 NEON] Add missing patterns for bitcast from or to v1f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 01:58:38 +00:00
Kevin Qin
4712264fb8 [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANE 
when lower build_vector if result value type mismatch with operand
value type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 08:06:14 +00:00
Kevin Qin
4905226c1c [AArch64 NEON] Fix a bug when lowering BUILD_VECTOR. 
DAG.getVectorShuffle() doesn't always return a vector_shuffle node.
If mask is the exact sequence of it's operand(For example, operand_0
is v8i8, and  the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly
return that operand. So a check is added here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197967 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 08:16:06 +00:00
Hao Liu
00a5490f87 [AArch64]Fix the pattern match failure for v1i8/v1i16/v1i32 types. 
Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them.
E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32:
     bitcast (load i32) to v1i32 -> load v1i32.
So this patch fixes such problems for load/dup instructions.
If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 02:51:28 +00:00
Hao Liu
60a21f2238 [AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 07:36:26 +00:00
Kevin Qin
24802f3f82 Fix Incorrect CHECK message [0-31]+ in test case. 
In regular expression, [0-31]+ equals to [0-3]+, not the number from
0 to 31. So change it to [0-9]+.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197113 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 02:19:13 +00:00
Hao Liu
e74a644b38 Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. 
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195424 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-22 08:47:22 +00:00
Kevin Qin
8263dcdf23 Implemented aarch64 neon intrinsic vcopy_lane with float type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 02:03:59 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 02:33:55 +00:00
Jiangning Liu
477fc628b3 Initial support for Neon scalar instructions. 
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 02:47:27 +00:00
Kevin Qin
e54360be01 Implement 3 AArch64 neon instructions : umov smov ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-17 02:21:02 +00:00