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2 Commits

Author SHA1 Message Date
Kevin Qin
3f8f3c9feb Fix a bug in DAGcombiner about zero-extend after setcc. 
For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-30 02:05:13 +00:00
Hao Liu
d9767021f8 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-15 08:26:11 +00:00