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3152 Commits

Author SHA1 Message Date
Jim Grosbach
376ce97bac Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to 
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 21:28:44 +00:00
Daniel Dunbar
3b9569e70d Hard to imagine there are still people using inferior compilers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 20:12:58 +00:00
Rafael Espindola
fd9493d74e Odd additional stub framework for the ARM MC ELF emission. 
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm

Patch by Jason Kim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 18:31:37 +00:00
Eric Christopher
1127c720ed Insert missing coherency in comment. Add a quick check for hardware 
divide support also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 06:08:12 +00:00
Eric Christopher
43b62beb4c Mass rename for Jim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-27 06:02:23 +00:00
Evan Cheng
5981fc6788 Fix IIC_iEXTAr itinerary class of Cortex-A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 01:09:28 +00:00
Evan Cheng
27fdcd1c95 Remove a unused instruction itinerary class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 01:06:02 +00:00
Evan Cheng
576a3968a2 Fix zero and sign extension instructions scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 00:49:35 +00:00
Evan Cheng
bd30ce4311 More pseudo instruction scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 22:41:41 +00:00
Evan Cheng
5be3922321 Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 22:03:46 +00:00
Jim Grosbach
433a5785cc Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 20:47:58 +00:00
Evan Cheng
fff606d7b2 Enable code placement optimization pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 19:07:23 +00:00
Evan Cheng
de0e11c8f3 Fix a potential null dereference bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 05:18:35 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:45:25 +00:00
Bob Wilson
2a6e616142 Set alignment operand for NEON VST instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:42:37 +00:00
Jim Grosbach
453900814e ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:33:56 +00:00
Jim Grosbach
b327e13740 #+4 --> #4 for consistency with other asm output 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c Fix formatting of output .s code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a Add isConditionalMove bits to X86 and ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 22:57:01 +00:00
Bob Wilson
40ff01a030 Set alignment operand for NEON VLD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 21:43:54 +00:00
Jim Grosbach
b2dda4bd34 never mind. I can't read, apparently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:42:17 +00:00
Evan Cheng
676e258366 Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:42:03 +00:00
Jim Grosbach
24e6f2f802 Fix opcode value for the 'trap' instruction, keeping the type suffix on the 
constant. Hopefully the non-Darwin bots will like it...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:32:40 +00:00
Jim Grosbach
5c49b69609 explicit 'unsigned long' on constant value. Hopefully make bots happier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:08:04 +00:00
Benjamin Kramer
c8ab9eb066 Unbreak build. Jim, please review. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:57:26 +00:00
Jim Grosbach
2e6ae13bf6 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:05:37 +00:00
Jim Grosbach
16c9a64c28 nuke unused var 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 17:58:00 +00:00
Evan Cheng
108c872466 If there are multiple unconditional branches terminating a block, eliminate all 
but the first one. Those will never be executed. There was logic to do this
but it was faulty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:54:40 +00:00
Jim Grosbach
637d89fe0e Add support for ELF PLT references for ARM MC asm printing. Adding a 
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 23:27:36 +00:00
Jim Grosbach
b6ec8cae3c Enable a few additional asserts in MC instruction lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 23:01:28 +00:00
Bob Wilson
b68987e4bf Change VDUPLANE DAG combiner to just return the result instead of calling 
CombineTo to avoid putting the result on the worklist.  I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 22:27:30 +00:00
Bob Wilson
0b8ccb8252 Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one 
of those.  Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 22:09:21 +00:00
Jim Grosbach
f0633e48eb add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 20:55:15 +00:00
Jim Grosbach
bfbe187593 Remove a few commented out bits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 20:32:34 +00:00
Jim Grosbach
00d01f1a42 Add PrintSpecial() handling for in ARM MC instruction printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 18:37:14 +00:00
Jim Grosbach
a2244cb387 Add MC instruction printer support for ARM and Thumb1 jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 17:39:48 +00:00
Jim Grosbach
205a5fa8e4 Add MC instruction printer support for TB[BH] style thumb2 jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 17:15:35 +00:00
Jim Grosbach
1b935a3d2e Clean up comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 16:45:13 +00:00
Evan Cheng
691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:49:07 +00:00
Jim Grosbach
882ef2b76a Add start of support for MC instruction printer of ARM jump tables. Filling in 
the rest of it is next up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:28:16 +00:00
Owen Anderson
8614167572 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes 
irrelevant, but add a new test for the new, improved functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 22:51:46 +00:00
Chris Lattner
52a261b3c1 fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 20:31:19 +00:00
Chris Lattner
fc448ff89b convert a couple more places to use the new getStore() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 18:51:21 +00:00
Bob Wilson
65ffec49f7 Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load 
and store intrinsics are represented with MemIntrinsicSDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 17:56:22 +00:00
Jim Grosbach
532baa5d53 Fix errant printing of [v]ldm instructions that aren't a pop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 16:45:31 +00:00
Gabor Greif
8ff9bb189c Fix buglet when the TST instruction directly uses the AND result. 
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 13:30:57 +00:00
Gabor Greif
04ac81d5db Move the search for the appropriate AND instruction 
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 12:01:15 +00:00
Chris Lattner
d1c24ed81c convert the targets off the non-MachinePointerInfo of getLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 06:44:06 +00:00
Chris Lattner
e72f2027e9 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo 
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4 convert targets to the new MF.getMachineMemOperand interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 04:39:43 +00:00