4 Commits

Author	SHA1	Message	Date
Kevin Qin	0a9ff8776b	[AArch64 NEON]Implment loading vector constant form constant pool. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197551 91177308-0d34-0410-b5e6-96231b3b80d8	2013-12-18 06:26:04 +00:00
Kevin Qin	24802f3f82	Fix Incorrect CHECK message [0-31]+ in test case. ... In regular expression, [0-31]+ equals to [0-3]+, not the number from 0 to 31. So change it to [0-9]+. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197113 91177308-0d34-0410-b5e6-96231b3b80d8	2013-12-12 02:19:13 +00:00
Ana Pazos	ddf4eb3d03	Fix pattern match for movi with 0D result ... Patch by Jiangning Liu. With some test case changes: - intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll. - New test cases to cover movi 1D scenario without using the intrinsic in test/CodeGen/AArch64/neon-mov.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196806 91177308-0d34-0410-b5e6-96231b3b80d8	2013-12-09 19:29:14 +00:00
Tim Northover	87773c318f	AArch64: add initial NEON support ... Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8	2013-08-01 09:20:35 +00:00