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3 Commits

Author SHA1 Message Date
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:40:25 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 19:13:08 +00:00
Jiangning Liu
959cd8f49b Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, 
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-09 02:20:27 +00:00