4 Commits

Author	SHA1	Message	Date
Daniel Sanders	f1ef27e6e3	[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8	2013-09-27 10:08:31 +00:00
Daniel Sanders	68831cbd41	[mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) ... The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8	2013-09-11 10:28:16 +00:00
Daniel Sanders	a65f149af6	[mips][msa] Summarize tests ... Adds a comment to the start of each test summarizing the area the test covers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189465 91177308-0d34-0410-b5e6-96231b3b80d8	2013-08-28 10:02:29 +00:00
Jack Carter	e2a9376b1b	[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) ... Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8	2013-08-15 12:24:57 +00:00