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719 Commits

Author SHA1 Message Date
Bill Wendling
651ad13d3c Add SDNode ordering to inlined asm and VA functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91876 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:25:10 +00:00
Bill Wendling
ec72e32fb0 Adding more assignment of ordering to SDNodes. This time in the "call" and 
generic copy functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91872 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:11:43 +00:00
Bill Wendling
e80ae836f2 Add ordering of SDNodes to LowerCallTo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:50:32 +00:00
Bill Wendling
d0283fa69f Now add ordering to SDNodes created by the massive intrinsic lowering function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91863 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:40:51 +00:00
Bill Wendling
856ff41079 To make things interesting, I added MORE code to set the ordering of 
SDNodes. This time in the load/store and limited-precision code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91860 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:12:37 +00:00
Bill Wendling
87710f04e5 Add more plumbing to assign ordering to SDNodes. Have the "getValue" method 
assign the ordering when called. Combine some of the ordering assignments to
keep things simple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91857 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 23:47:40 +00:00
Bill Wendling
e1a9042041 More ordering plumbing. This time for GEP. I need to remember to assign 
orderings to values returned by getValue().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 23:10:19 +00:00
Bill Wendling
b85b6e8882 Another incremental check-in for assigning ordering to SDNodes. This time for 
shuffle and insert vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 22:42:14 +00:00
Bill Wendling
49fcff8a5d Assign ordering to more instructions. Incremental check-in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91846 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 22:30:11 +00:00
Bill Wendling
0777e92721 - Add a bit more plumbing assigning an order to SDNodes. 
- Modify the "dump" method to emit the order of an SDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91845 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 21:59:52 +00:00
Bill Wendling
3b7a41ce90 First wave of plumbing for assigning an ordering to SDNodes. This takes care of 
a lot of the branching instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 19:59:38 +00:00
Bill Wendling
b4e6a5df5d Changes from review: 
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
  doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 23:32:53 +00:00
Bob Wilson
5afffaed5c Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:03:29 +00:00
Bob Wilson
266d945fff Fix a comment grammaro. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91584 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 05:07:36 +00:00
Daniel Dunbar
819309efec Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 20:10:05 +00:00
Daniel Dunbar
222518d0bb Revert "Initial work on disabling the scheduler. This is a work in progress, and 
this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 10:56:02 +00:00
Bill Wendling
614407a9d2 Initial work on disabling the scheduler. This is a work in progress, and this 
stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91392 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 01:54:51 +00:00
Dan Gohman
a4f9cc4e55 Fix the result type of SELECT nodes lowered from Select instructions with 
aggregate return values. This fixes PR5754.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 19:50:50 +00:00
Dan Gohman
2048b85c7c Rename SelectionDAGLowering to SelectionDAGBuilder, and rename 
SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89681 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 18:04:58 +00:00