Bradley Smith
42c672649c
[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:36 +00:00
Bradley Smith
9a9fa81c1a
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:07 +00:00
Bradley Smith
f797751ca0
[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:35 +00:00
Bradley Smith
dcb9231b8a
[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:56 +00:00
Bradley Smith
fb7edfa9a5
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
Bradley Smith
01229fa891
[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:27 +00:00
Bradley Smith
a493b7786a
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:11 +00:00
Bradley Smith
35b8c724c7
[ARM64] STRHro and STRBro were not being decoded at all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:49 +00:00
Bradley Smith
6307036c7c
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:45 +00:00
Bradley Smith
7ac29214ce
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:38 +00:00
Aaron Ballman
103683c4cb
Fixing warnings in the MSVC build. No functional changes intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 12:22:20 +00:00
Alexey Samsonov
285606027b
Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 07:59:33 +00:00
Chandler Carruth
3734a337e9
[ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
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no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.
Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 11:07:40 +00:00
Tim Northover
7b837d8c75
ARM64: initial backend import
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This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
