21182 Commits

Author SHA1 Message Date
Manman Ren
c1e2b2582c Debug Info: In DIBuilder, the derived-from field of DICompositeType
is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192251 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 23:28:51 +00:00
Manman Ren
78c2f9b8cf Debug Info: In DIBuilder, the derived-from field of DIDerivedType
is updated to use DITypeRef.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 22:56:31 +00:00
Chad Rosier
c976500793 [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 22:09:04 +00:00
Chad Rosier
3dfe644f7b [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 20:43:30 +00:00
Manman Ren
875857953f Debug Info: update testing to reflect r192018.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 20:06:43 +00:00
Reed Kotler
78f8339f35 Add fabsf to the list of inlined functions; otherwise
Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 19:55:01 +00:00
Matt Arsenault
194d437f11 Add some xfaild R600 tests.
These are bugs to fix later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 18:06:36 +00:00
Reed Kotler
b359bda93d Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 17:32:33 +00:00
Craig Topper
75172ad6f2 Fix a typo in the mattr part of the run line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 06:12:26 +00:00
Craig Topper
d8feb1f9a5 Explicitly disable AVX on a bunch of tests so they won't fail on AVX machines post r192171.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 06:06:57 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 05:53:50 +00:00
Adrian Prantl
d79f6f786a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192158 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 02:30:54 +00:00
Adrian Prantl
a204ac9e90 typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 02:28:20 +00:00
Adrian Prantl
82c7414448 Reduce testcase from 1r92011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 02:21:44 +00:00
Akira Hatanaka
d56cba0b4b [mips] Test case for r192124.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 21:32:57 +00:00
Arnold Schwaighofer
1ee3c0008b LoopVectorize: External uses must use the last value in a reduction cycle
Otherwise, we don't perform operations that would have been performed on
the scalar version.

Fixes PR17498.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 21:05:43 +00:00
Reed Kotler
42be15fcbe Add Mips16 patterns for sign extend byte and sign extend halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 20:46:19 +00:00
Manman Ren
fb92f46459 Struct byval: use the correct alignment for loads generated to load
from struct byval to registers.

We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.

The fix is to pass the alignment of the struct byval.

rdar://problem/15144402


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:47:53 +00:00
Benjamin Kramer
51a8280fbb X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64.
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:11:35 +00:00
Alexey Samsonov
23eb90714b Revert r191834 until we measure the effect of this benchmarks and maybe find a better way to fix it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 19:03:24 +00:00
Matt Arsenault
c4a8c07f64 Change objectsize intrinsic to accept different address spaces.
Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 18:06:48 +00:00
Amara Emerson
ca7b2d08d7 [ARM] Improve build attributes emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:55:23 +00:00
Chad Rosier
2aeb4771a6 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:36:15 +00:00
Joey Gouly
fbe4f5afce [ARMv8] Add some disassembly tests for Thumb sevl/sevl.w
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 16:13:03 +00:00
Tim Northover
cf3e4cb29a ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 11:10:47 +00:00
Simon Atanasyan
c84c742edd [Mips] Teach llvm-readobj to print MIPS-specific ELF program headers.
The patch reviewed by Michael Spencer.
http://llvm-reviews.chandlerc.com/D1846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 08:58:27 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 07:19:47 +00:00
Craig Topper
8fdba75d5b Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 05:42:48 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 04:28:06 +00:00
Rafael Espindola
2def17935c Add support for aliases with linkonce_odr.
This will be used to extend constructor aliases in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 15:10:43 +00:00
Benjamin Kramer
fb7cb838b9 Force a CPU that doesn't have AVX, otherwise this test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 13:52:41 +00:00
Benjamin Kramer
d9f7a185e3 X86: Don't fold spills into SSE operations if the stack is unaligned.
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 13:48:22 +00:00
Elena Demikhovsky
714319a169 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 13:11:09 +00:00
Venkatraman Govindaraju
79c5e0c5ca [Sparc] Do not emit nop after fcmp* instruction with V9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192056 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 07:06:44 +00:00
Elena Demikhovsky
a6269ee5fb AVX-512: fixed shuffle lowering
in case of BLEND and added VSHUFPS patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 06:11:18 +00:00
Venkatraman Govindaraju
20b10abf4e [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju
bb0ec9840b [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
addx/subx does not modify conditional codes whereas addxcc/subxx does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 02:11:10 +00:00
Benjamin Kramer
87855d3013 Emit a better error when running out of registers on inline asm.
The most likely case where this error happens is when the user specifies
too many register operands. Don't make it look like an internal LLVM bug
when we can see that the error is coming from an inline asm instruction.
For other instructions we keep the "ran out of registers" error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:33:37 +00:00
Craig Topper
22abf7e17f Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:22:59 +00:00
Craig Topper
e2522fd06c Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 17:17:53 +00:00
Rafael Espindola
5e195a4c8d Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 16:42:21 +00:00
Jiangning Liu
beb6afa843 Implement aarch64 neon instruction set AdvSIMD (Across).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 08:22:10 +00:00
Rafael Espindola
e8bcb9dd99 Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 02:58:36 +00:00
Venkatraman Govindaraju
a8147756d6 [Sparc] Use correct alignment while loading/storing fp128 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 02:29:47 +00:00
Andrew Kaylor
b64c573649 Updating XFAILs for recent GOT tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192022 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 01:56:50 +00:00
Andrew Kaylor
95dea01cb6 Adding tests for multiple GOTs with MCJIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 01:53:19 +00:00
Manman Ren
c664d76716 Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_type
is updated to use DITypeRef.

Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static
helper functions in DwarfCompileUnit. We already have a static helper function
"isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to
resolve the derived-from field. All three functions need to go across link
for derived-from fields, so we need to get hold of a type identifier map.

A pointer to DwarfDebug is also added to DbgVariable in order to resolve the
derived-from field.

Debug info verifier is updated to check a derived-from field is a TypeRef.
Verifier will not go across link for derived-from fields, in debug info finder,
we go across the link to add derived-from fields to types.

Function getDICompositeType is only used by dragonegg and since dragonegg does
not generate identifier for types, we use an empty map to resolve the
derived-from field.

When printing a derived-from field, we use DITypeRef::getName to either return
the type identifier or getName of the DIType.

A paired commit at clang is required due to changes to DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192018 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 01:43:03 +00:00
Venkatraman Govindaraju
b648122c5f [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 00:31:41 +00:00
Adrian Prantl
eacbfd1d51 Debug info: Don't crash in SelectionDAGISel when a vreg that is being
pointed to by a dbg_value belonging to a function argument is eliminated
during instruction selection.
rdar://problem/15094721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 00:08:27 +00:00
Venkatraman Govindaraju
1c9524b624 [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 23:54:30 +00:00