49875 Commits

Author SHA1 Message Date
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00
Andrew Trick
3af7a67629 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:06:13 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:46:54 +00:00
Eric Christopher
33fe8eb46c Remove from cmake too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:38:04 +00:00
Eric Christopher
eae5a13078 Remove more of llvmc and dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:34:27 +00:00
Jim Grosbach
6053cd956f Thumb2 assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:30:45 +00:00
Jim Grosbach
8c9898454c Remove incorrect comments. These are not disassmebly only patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:26:34 +00:00
Jim Grosbach
ab3bf97fe0 Thumb2 assembly parsing and encoding for UQASX/UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:18:52 +00:00
Jim Grosbach
abb8aacef2 Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:10:37 +00:00
Jim Grosbach
26215425da Thumb CPS definition is not disassembler only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:00:06 +00:00
Jim Grosbach
0efe213ed5 Thumb2 range check on CPS mode immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:58:31 +00:00
Owen Anderson
d9346fbb06 tMOVSr is not allowed in an IT block either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e CPS instructions are UNPREDICTABLE inside IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:47:10 +00:00
Jim Grosbach
32f36899e9 Tidy up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:38:34 +00:00
Bruno Cardoso Lopes
d91c6e058b Fix PR10949. Fix the encoding of VMOVPQIto64rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
97136c922e Based on the small opt Zvi's patch was trying to achieve, eliminate
128-bit undef subvector insertion into a 256-bit vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:36:50 +00:00
Jim Grosbach
d5d0e81a4b Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:31:02 +00:00
Bill Wendling
a846585050 Revert r140083 and r140084 until buildbots can be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:30:41 +00:00
Jim Grosbach
6729c48b94 Thumb2 assembly parsing and encoding for UHASX/UHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:13:25 +00:00
Jim Grosbach
4032eaf98c Thumb2 assembly parsing and encoding for UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:05:22 +00:00
Bill Wendling
ad027053fe If we are extracting a basic block that ends in an invoke call, we must also
extract the landing pad block. Otherwise, there will be a situation where the
invoke's unwind edge lands on a non-landing pad.

We also forbid the user from extracting the landing pad block by itself. Again,
this is not a valid transformation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:00:52 +00:00
Owen Anderson
04c7877894 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:21:13 +00:00
Eli Friedman
c6b8ba8673 Fix an infinite loop where a transform in InstCombiner::visitAnd claims a construct is changed when it is not. (See included testcase.)
Patch by Xiaoyi Guo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 21:58:15 +00:00
Bruno Cardoso Lopes
97dc60b759 Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
PR10955 and PR10948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 21:29:24 +00:00
Eric Christopher
627445f3e6 Rename LLVM_MULTITHREADED define and fix build without threads.
Patch by Arrowdodger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:43:23 +00:00
Jim Grosbach
bc80e94865 Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:31:59 +00:00
Jim Grosbach
326efe5891 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:29:33 +00:00
Akira Hatanaka
da7f5f1c1d Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:26:02 +00:00
Benjamin Kramer
586a55a290 Silence -Wsign-compare warnings from GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:08:54 +00:00
Owen Anderson
061c3c4506 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 20:00:02 +00:00
Eli Friedman
c3d3598425 Fix a typo in the bitcode reader in the handling of atomic stores. Reported by David Meyer on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 19:41:28 +00:00
Jim Grosbach
fb12f35545 ARM asm parsing should handle pre-indexed writeback w/o immediate.
For example, 'ldrb r9, [sp]!' is odd, but valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:42:21 +00:00
Owen Anderson
ecd1c55790 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:07:10 +00:00
Jim Grosbach
8a8d28b039 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 17:56:37 +00:00
Benjamin Kramer
a182be9b6c MCInstrAnalysis: Don't crash on instructions with no operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 17:56:00 +00:00
Andrew Trick
24f48ece52 [indvars] Fix PR10946: SCEV cannot handle Vector IVs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 17:54:39 +00:00
NAKAMURA Takumi
92ec8e1427 Add Win32 support to llvm::llvm_execute_on_thread(). Thanks to Aaron Ballman!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 07:41:43 +00:00
Nadav Rotem
ca6f296b48 Fix typos in my prev commit, found by Tobi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 19:00:23 +00:00
Nadav Rotem
354efd88db setOperationAction should be done on the return value of the type, not the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 14:57:03 +00:00
Nadav Rotem
91e43fd17a When promoting integer vectors we often create ext-loads. This patch adds a
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 10:39:32 +00:00
Nadav Rotem
b6266fb602 white space cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 10:29:29 +00:00
Craig Topper
89af15ee11 Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-18 08:03:58 +00:00
Duncan Sands
6bcd2196e5 Synthesize x86 max/min instructions also for vectors (i.e. produce
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-17 16:49:39 +00:00
Bruno Cardoso Lopes
2c693dc126 Describe more AVX 128-bit convert instructions without patterns to have
mayLoad = 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:41:29 +00:00
Owen Anderson
cb77551927 Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431 Fix bitfield decoding based on Eli's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:04:48 +00:00
Jim Grosbach
f67e8554bf Thumb2 assembly parsing and encoding for SUB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:58:42 +00:00
Owen Anderson
e4f2df945a Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:29:48 +00:00