6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity
100,346 Commits 39 Branches 0 Tags 277 MiB
4959a2d878
Commit Graph

4 Commits

Author SHA1 Message Date
Tilmann Scheller
2f184eaf89 [ARM] Use FileCheck instead of grep for ARM LDRD negative tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 17:31:26 +00:00
Tilmann Scheller
9724873c31 [ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers. 
See ARM ARM A8.8.72.

Violating this constraint results in unpredictable behavior.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 16:11:48 +00:00
Tilmann Scheller
6206a132a7 [ARM] Assembler: Add more negative tests for ARM LDRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 13:04:22 +00:00
Tilmann Scheller
cca1146119 ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands. 
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 13:28:17 +00:00