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14924 Commits

Author SHA1 Message Date
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Chad Rosier
11add26ec2 Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:31:03 +00:00
Chad Rosier
6d267449ac Loosen test by using REs. Approved by Devang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:25:38 +00:00
Andrew Trick
95bc85e4ee Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:18:09 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Devang Patel
48857eb179 Move X86 specific test in X86 directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144395 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 18:13:19 +00:00
Devang Patel
2d5bbef415 Move X86 specific test in X86 directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 18:10:38 +00:00
Dan Bailey
96e6458903 allow non-device function calls in PTX when natively handling device-side printf 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144388 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 14:45:12 +00:00
Craig Topper
46154eb6fd Add lowering for AVX2 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 07:39:23 +00:00
Chad Rosier
a07d3fc693 Add support for using immediates with select instructions. 
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 06:20:39 +00:00
Eli Friedman
15f58c56e9 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:16:38 +00:00
Eli Friedman
b80f778bd3 Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which 
lead to it trying to re-mark a value marked as a constant with a different value.  It also appears to trigger very rarely.

Fixes PR11357.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 01:16:15 +00:00
Chad Rosier
4e89d97e3a Add support for using MVN to materialize negative constants. 
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:36:21 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Rafael Espindola
01b55b4a80 Check in getOrCreateSubprogramDIE if a declaration exists and if so output 
it first.

This is a more general fix to pr11300.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:34:29 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Chad Rosier
16455ce1a4 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 21:09:49 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
NAKAMURA Takumi
bd165eac9d test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin. 
I guess it expects -relocation-model=pic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 14:18:59 +00:00
Evan Cheng
623a7e146b Use a bigger hammer to fix PR11314 by disabling the "forcing two-address 
instruction lower optimization" in the pre-RA scheduler.

The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.

Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 07:43:16 +00:00
Chad Rosier
6cba97c555 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:30:39 +00:00
Jakob Stoklund Olesen
17afb06648 Strip old implicit operands after foldMemoryOperand. 
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:17:03 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Eli Friedman
14e809c872 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:36:02 +00:00
Pete Cooper
5ccb0825ed DeadStoreElimination can now trim the size of a store if the end of the store is dead. 
Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.

Fixes <rdar://problem/10140300>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144239 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:07:35 +00:00
Eli Friedman
0948f0acca Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 22:25:12 +00:00
Nadav Rotem
c6c7e85a71 AVX2: Add patterns for variable shift operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 21:22:13 +00:00
Chad Rosier
a7a996b98d Use REs to remove dependencies on the register allocation order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 20:06:13 +00:00
Duncan Sands
ef0b3ca3a8 Speculatively revert commit 144124 (djg) in the hope that the 32 bit 
dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages).  Original commit message:

Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 14:20:48 +00:00
Nadav Rotem
bb539bf973 Add AVX2 support for vselect of v32i8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 13:21:28 +00:00
Craig Topper
b80ada98c5 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 09:37:21 +00:00
Craig Topper
0a15035f52 Add instruction selection for AVX2 integer comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 08:06:13 +00:00
Craig Topper
aaa643c70e Add AVX2 instruction lowering for add, sub, and mul. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 07:28:55 +00:00
Nick Lewycky
89d093d5b6 Don't forget to check FlagNW when determining whether an AddRecExpr will wrap 
or not. Patch by Brendon Cahoon!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 07:11:37 +00:00
Chad Rosier
2f2fe417f9 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 03:22:02 +00:00
Jakob Stoklund Olesen
f4c4768fb2 Collapse DomainValues across loop back-edges. 
During the initial RPO traversal of the basic blocks, remember the ones
that are incomplete because of back-edges from predecessors that haven't
been visited yet.

After the initial RPO, revisit all those loop headers so the incoming
DomainValues on the back-edges can be properly collapsed.

This will properly fix execution domains on software pipelined code,
like the included test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 01:06:56 +00:00
Dan Gohman
9cae2d2225 Add a hack to the scheduler to disable pseudo-two-address dependencies in 
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:29:06 +00:00
Evan Cheng
3568a1051e Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:21:09 +00:00
Eli Friedman
7781ae5be5 Fix code to match comment. Fixes PR11340, a regression from r143209. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 21:08:02 +00:00
Pete Cooper
2d76a78462 LICM pass now understands invariant load metadata. Nothing generates this yet so it will currently never get used in real tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 19:30:00 +00:00
Pete Cooper
d9eb920aa4 Adding test for machine-licm operating on invariant load instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 19:06:53 +00:00
Lang Hames
5207bf2177 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 18:56:23 +00:00
NAKAMURA Takumi
a422294ab1 test/CodeGen/X86/vec_shuffle-39.ll: Add explicit -mtriple=x86_64-linux. Passing packed value is not compatible on Win32 x64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 03:46:39 +00:00
NAKAMURA Takumi
916d6441e1 test/CodeGen/X86/vec_shuffle-38.ll: Relax expression for Win32 x64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144067 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 03:46:32 +00:00
NAKAMURA Takumi
5fb870d861 test/CodeGen/X86/vec_shuffle.ll: Add explicit -mtriple=i686-linux. We may see some suboptimal frame (%ebp) emission on certain hosts. Possible [PR11031] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 03:46:25 +00:00
Eli Friedman
9f1f26aefa Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:43:53 +00:00
Eli Friedman
2efa35f779 Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318. 
Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 01:25:24 +00:00
Evan Cheng
7bc389b6b0 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:31:58 +00:00
Bill Wendling
0d69097779 Convert to the new EH model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 00:23:01 +00:00