Commit Graph

9 Commits

Author SHA1 Message Date
Tom Stellard
f5be357d37 AMDGPU/SI: Select mad patterns to v_mac_f32
The two-address instruction pass will convert these back to v_mad_f32
if necessary.

Differential Revision: http://reviews.llvm.org/D11060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:47:57 +00:00
Tom Stellard
e05910e677 AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:27 +00:00
Tom Stellard
0be7d0cf17 AMDPGU/SI: Use correct resource descriptors for VI on HSA
Summary: We need to set MTYPE = 2 for VI shaders when targeting the HSA runtime.

Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D10777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:42 +00:00
Marek Olsak
e874345be4 AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
If pseudoToMCOpcode failed, we would return the original opcode, so operands
would be swapped, but the instruction would remain the same.
It resulted in LSHLREV a, b ---> LSHLREV b, a.

This fixes Glamor text rendering and
piglit/arb_sample_shading-builtin-gl-sample-mask on VI.

This is a candidate for stable branches.

v2: the test was simplified by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240824 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 20:29:10 +00:00
Eric Christopher
933d2bd391 Fix "the the" in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240112 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-19 01:53:21 +00:00
Sanjoy Das
319c91bbb0 [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.
Summary:

TargetInstrInfo::getLdStBaseRegImmOfs to
TargetInstrInfo::getMemOpBaseRegImmOfs and implement for x86.  The
implementation only handles a few easy cases now and will be made more
sophisticated in the future.

This is NFCI: the only user of `getLdStBaseRegImmOfs` (now
`getmemOpBaseRegImmOfs`) is `LoadClusterMotion` and `LoadClusterMotion`
is disabled for x86.

Reviewers: reames, ab, MatzeB, atrick

Reviewed By: MatzeB, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239741 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:14 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tom Stellard
b1162b8d4b Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:53 +00:00
Tom Stellard
23dc769a9b AMDGPU: Add core backend files for R600/SI codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:08 +00:00