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2670 Commits

Author SHA1 Message Date
Nate Begeman
17c275ff2c Make emission of jump tables a bit less conservative; they are now required 
to be only 31.25% dense, rather than 75% dense.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28165 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-08 16:51:36 +00:00
Nate Begeman
5c742681ed Fix PR772 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28161 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-08 01:35:01 +00:00
Chris Lattner
822db93e57 Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us 
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28155 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 23:48:13 +00:00
Chris Lattner
e60351bb72 Add some more sign propagation cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28154 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 23:40:29 +00:00
Chris Lattner
310b578023 Simplify some code, add a couple minor missed folds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28152 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 23:06:26 +00:00
Chris Lattner
b9ebacdb4d constant fold sign_extend_inreg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28151 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 23:05:41 +00:00
Chris Lattner
541a24f7af remove cases handled elsewhere 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28150 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 22:43:44 +00:00
Chris Lattner
d6f7fe76a6 Add some more simple sign bit propagation cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28149 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 22:39:59 +00:00
Jeff Cohen
d43b18d9e4 Fix some loose ends in MASM support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28148 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 21:27:14 +00:00
Chris Lattner
ee4ea92358 Use the new TargetLowering::ComputeNumSignBits method to eliminate 
sign_extend_inreg operations.  Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:

short test(short X, short x) {
  int Y = X+x;
  return (Y >> 1);
}
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

into:

_test:
        add r2, r3, r4
        srawi r3, r2, 1
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test:
        add r2, r3, r4
        srawi r2, r2, 1
        extsh r3, r2
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r2, r2, 1
        extsh r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28146 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 09:30:03 +00:00
Chris Lattner
5c3e21d687 Add some really really simple code for computing sign-bit propagation. 
This will certainly be enhanced in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28145 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 09:27:13 +00:00
Chris Lattner
f0df8824eb When inserting casts, be careful of where we put them. We cannot insert 
a cast immediately before a PHI node.

This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 09:10:37 +00:00
Chris Lattner
c93dfda905 Fold (trunc (srl x, c)) -> (srl (trunc x), c) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28138 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-06 00:11:52 +00:00
Chris Lattner
b72773bb88 Fold trunc(any_ext). This gives stuff like: 
27,28c27
<       movzwl %di, %edi
<       movl %edi, %ebx
---
>       movw %di, %bx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28137 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 22:56:26 +00:00
Chris Lattner
06afe07037 Shrink shifts when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 22:53:17 +00:00
Chris Lattner
fe8babf689 Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28135 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 22:32:12 +00:00
Chris Lattner
1c05997bd8 Indent multiline asm strings more nicely 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28132 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 21:47:05 +00:00
Chris Lattner
e564dbb51c Fold (fpext (load x)) -> (extload x) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28130 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 21:34:35 +00:00
Chris Lattner
903236468c More aggressively sink GEP offsets into loops. For example, before we 
generated:

        movl 8(%esp), %eax
        movl %eax, %edx
        addl $4316, %edx
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, (%edx)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
        movl %edx, 4460(%eax)
        ret
...

Now we generate:

        movl 8(%esp), %eax
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, 4316(%eax)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
        movl %ecx, 4460(%eax)
        ret

... which uses one fewer register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28129 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 21:17:49 +00:00
Chris Lattner
0d8dae749c Fold some common code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28124 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 06:32:04 +00:00
Chris Lattner
540121f1ec Implement: 
// fold (and (sext x), (sext y)) -> (sext (and x, y))
  // fold (or  (sext x), (sext y)) -> (sext (or  x, y))
  // fold (xor (sext x), (sext y)) -> (sext (xor x, y))
  // fold (and (aext x), (aext y)) -> (aext (and x, y))
  // fold (or  (aext x), (aext y)) -> (aext (or  x, y))
  // fold (xor (aext x), (aext y)) -> (aext (xor x, y))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28123 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 06:31:05 +00:00
Chris Lattner
a3dc3f692c Pull and through and/or/xor. This compiles some bitfield code to: 
mov EAX, DWORD PTR [ESP + 4]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        or EDX, ECX
        and EDX, -2147483648
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        ret

instead of:

        sub ESP, 4
        mov DWORD PTR [ESP], ESI
        mov EAX, DWORD PTR [ESP + 8]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        mov ESI, ECX
        and ESI, -2147483648
        and EDX, -2147483648
        or EDX, ESI
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        mov ESI, DWORD PTR [ESP]
        add ESP, 4
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28122 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 06:10:43 +00:00
Chris Lattner
5ffc066912 Implement a variety of simplifications for ANY_EXTEND. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28121 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 05:58:59 +00:00
Chris Lattner
35e5c14b80 Factor some code, add these transformations: 
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
  // fold (or  (trunc x), (trunc y)) -> (trunc (or  x, y))
  // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28120 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 05:51:50 +00:00
Jeff Cohen
4b75e73791 Fix VC++ compilation error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28117 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 01:47:05 +00:00
Chris Lattner
7e598096ea Sink noop copies into the basic block that uses them. This reduces the number 
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28115 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 01:04:50 +00:00
Chris Lattner
6e994b7492 Final pass of minor cleanups for MachineInstr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28110 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 19:36:09 +00:00
Evan Cheng
14a6db8bd9 Initial support for register pressure aware scheduling. The register reduction 
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28108 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 19:16:39 +00:00
Chris Lattner
943b5e117f Remove redundancy and a level of indirection when creating machine operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28107 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 19:14:44 +00:00
Chris Lattner
8b915b4ed2 Remove and simplify some more machineinstr/machineoperand stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 18:16:01 +00:00
Chris Lattner
2d90ac7ca6 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 18:05:43 +00:00
Chris Lattner
e53f4a055f Move some methods out of MachineInstr into MachineOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 17:52:23 +00:00
Chris Lattner
63b3d7113d There shalt be only one "immediate" operand type! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 17:21:20 +00:00
Chris Lattner
ceb408f6a2 Change "value" in MachineOperand to be a GlobalValue, as that is the only 
thing that can be in it.  Remove a dead method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28098 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 17:02:51 +00:00
Chris Lattner
4efeab208c Remove a bunch more dead V9 specific stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28094 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 01:26:39 +00:00
Chris Lattner
ea50fabfd4 Remove a bunch more SparcV9 specific stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 01:15:02 +00:00
Chris Lattner
34fb2cad46 Remove some more V9-specific stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28092 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 00:49:59 +00:00
Chris Lattner
10f3597c4e Remove some more unused stuff from MachineInstr that was leftover from V9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28091 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 00:44:25 +00:00
Chris Lattner
b4432f3d47 Suck block address tracking out of targets into the JIT Emitter. This 
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28082 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 17:10:41 +00:00
Nate Begeman
f4360a4789 Finish up the initial jump table implementation by allowing jump tables to 
not be 100% dense.  Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28079 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 03:48:02 +00:00
Evan Cheng
c9a83a45ba Bottom up register pressure reduction work: clean up some hacks and enhanced 
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28076 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 02:10:45 +00:00
Owen Anderson
a69571c799 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 01:29:57 +00:00
Chris Lattner
af1563fb62 Change the BasicBlockAddrs map to be a vector, indexed by MBB number. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28069 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 00:32:55 +00:00
Chris Lattner
f75f9be3fb Several related changes: 
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
   from the MachineCodeEmitter interface, and reducing the amount of target-
   specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
   *right* next to the functions that they belong to, instead of in a separate
   pool of memory.  This makes all memory for a function be contiguous, and
   means the JITEmitter only tracks one block of memory now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28065 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 23:22:24 +00:00
Chris Lattner
f5d438c1f0 Do not make the JIT memory manager manage the memory for globals. Instead 
just have the JIT malloc them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28062 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 21:57:51 +00:00
Chris Lattner
43b429b059 Refactor the machine code emitter interface to pull the pointers for the current 
code emission location into the base class, instead of being in the derived classes.

This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments.  This implements feature request #1 of PR469.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28059 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 18:27:26 +00:00
Nate Begeman
9d51eeb8bc Print function number instead of name 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28057 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 17:36:46 +00:00
Chris Lattner
b0cc79d45b Remove dead method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28055 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 17:20:28 +00:00
Chris Lattner
3a9cfbaf86 Remove the debug machine code emitter. The "FilePrinterEmitter" is more 
useful for debugging.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28051 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 16:59:24 +00:00
Nate Begeman
cdf38c4edb Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28050 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 05:37:32 +00:00
Jeff Cohen
51b776d259 De-virtualize SwitchSection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28047 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 03:58:45 +00:00
Jeff Cohen
c6a057b04d De-virtualize EmitZeroes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28046 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 03:46:13 +00:00
Jeff Cohen
c884db47f1 Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28044 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 01:16:28 +00:00
Chris Lattner
229924a79f Fix a latent bug that my spiller patch last week exposed: we were leaving 
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 22:03:24 +00:00
Chris Lattner
8a18c13fa5 When promoting a load to a reg-reg copy, where the load was a previous 
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 21:17:10 +00:00
Chris Lattner
35f2705e3d Remove previous patch, which wasn't quite right. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 21:16:03 +00:00
Evan Cheng
22608c2d1f Dis-favor stores more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 09:20:44 +00:00
Evan Cheng
f229a5d4be Bottom up register-pressure reduction scheduler now pushes store operations 
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 09:14:40 +00:00
Evan Cheng
3766d66b91 Didn't mean ScheduleDAGList.cpp to make the last checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 08:56:34 +00:00
Evan Cheng
10dbd3ead8 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 08:54:57 +00:00
Chris Lattner
c80c43eee0 Format #APP lines a bit nicer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 04:11:03 +00:00
Evan Cheng
200370fb56 Local spiller kills a store if the folded restore is turned into a copy. 
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-30 08:41:47 +00:00
Chris Lattner
25c344a758 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c 
with some changes I have to the new CFE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 23:33:20 +00:00
Evan Cheng
55d0fa1bfa Remove the temporary option: -no-isel-fold-inflight 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 18:54:11 +00:00
Evan Cheng
020c41f21e TargetLowering::LowerArguments should return a VBIT_CONVERT of 
FORMAL_ARGUMENTS SDOperand in the return result vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 05:25:15 +00:00
Chris Lattner
ba1fc3daf7 Mapping of physregs can make it so that the designated and input physregs are 
the same.  In this case, don't emit a noop copy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 04:43:18 +00:00
Evan Cheng
552c4a8494 Added a temporary option -no-isel-fold-inflight to control whether a "inflight" 
node can be folded.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 02:09:19 +00:00
Chris Lattner
addc55af6c When we have a two-address instruction where the input cannot be clobbered 
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 01:46:50 +00:00
Evan Cheng
f7179bb56e Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses 
(VAND, VADD, etc.). Legalizer will assert otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-27 08:29:42 +00:00
Chris Lattner
a83385fb7b Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and 
PR748.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27987 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-27 05:01:07 +00:00
Evan Cheng
3b0d286d00 Don't forget return void. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27974 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-25 23:03:35 +00:00
Nate Begeman
9453eea49b Fix the updating of the machine CFG when a PHI node was in a successor of 
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27952 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-23 06:26:20 +00:00
Nate Begeman
3700a4d3a2 Code cleanup associated with jump tables, thanks to Chris for noticing 
these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27950 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 23:52:35 +00:00
Nate Begeman
05f9466cf0 Turn of jump tables for a bit, there are still some issues to work out with 
updating the machine CFG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27949 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 23:51:56 +00:00
Nate Begeman
37efe67645 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 18:53:45 +00:00
Chris Lattner
4a1cd9c61e The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap 
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27933 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-21 17:16:16 +00:00
Chris Lattner
ef027f940c Fix a couple more memory issues 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-21 15:32:26 +00:00
Chris Lattner
fedced7bc3 Fix a really subtle and obnoxious memory bug that caused issues with an 
llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27922 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 23:55:59 +00:00
Chris Lattner
1b87c42c82 This field no longer exists 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27899 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 18:32:41 +00:00
Chris Lattner
02e5f8dcda Remove some of the obvious V9-specific cruft 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27893 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 18:08:53 +00:00
Evan Cheng
44f1f09b4e Turn a VAND into a VECTOR_SHUFFLE is applicable. 
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27874 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 08:56:16 +00:00
Chris Lattner
62b5772959 Implement folding of a bunch of binops with undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 05:39:12 +00:00
Chris Lattner
89a1b380a4 Simplify some code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27846 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-19 23:17:50 +00:00
Chris Lattner
80edfb3af5 Fix handling of calls in functions that use vectors. This fixes a crash on 
the code in GCC PR26546.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27780 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 22:10:08 +00:00
Chris Lattner
48d7c069c7 Add a MachineInstr::eraseFromParent convenience method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27775 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 21:35:41 +00:00
Chris Lattner
8d5a894501 Codegen insertelement with constant insertion points as scalar_to_vector 
and a shuffle.  For this:

void %test2(<4 x float>* %F, float %f) {
        %tmp = load <4 x float>* %F             ; <<4 x float>> [#uses=2]
        %tmp3 = add <4 x float> %tmp, %tmp              ; <<4 x float>> [#uses=1]
        %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2               ; <<4 x float>> [#uses=2]
        %tmp6 = add <4 x float> %tmp2, %tmp2            ; <<4 x float>> [#uses=1]
        store <4 x float> %tmp6, <4 x float>* %F
        ret void
}

we now get this on X86 (which will get better):

_test2:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, %xmm1
        shufps $3, %xmm1, %xmm1
        movaps %xmm0, %xmm2
        shufps $1, %xmm2, %xmm2
        unpcklps %xmm1, %xmm2
        movss 8(%esp), %xmm1
        unpcklps %xmm1, %xmm0
        unpcklps %xmm2, %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        ret

instead of:

_test2:
        subl $28, %esp
        movl 32(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%esp)
        movss 36(%esp), %xmm0
        movss %xmm0, 8(%esp)
        movaps (%esp), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        addl $28, %esp
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27765 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 19:21:01 +00:00
Chris Lattner
2efce0a589 Add support for promoting stores from one legal type to another, allowing us 
to write one pattern for vector stores instead of 4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27730 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-16 01:36:45 +00:00
Chris Lattner
547a16f273 Make these predicates return true for bit_convert(buildvector)'s as well as 
buildvectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27723 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-15 23:38:00 +00:00
Chris Lattner
3824e50b1e Make this assertion better 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27695 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-14 06:08:35 +00:00
Reid Spencer
60d07eeffe Expand some code with temporary variables to rid ourselves of the warning 
about "dereferencing type-punned pointer will break strict-aliasing rules"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27671 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-13 18:29:58 +00:00
Evan Cheng
cc9876124e Promote vector AND, OR, and XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27632 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 21:20:24 +00:00
Evan Cheng
41f6cbbeb2 Vector type promotion for ISD::LOAD and ISD::SELECT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27606 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 16:33:18 +00:00
Chris Lattner
fdfded5588 Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27604 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 16:20:43 +00:00
Chris Lattner
9d956250f5 Don't memoize vloads in the load map! Don't memoize them anywhere here, let 
getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27602 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 03:25:41 +00:00
Evan Cheng
98f8aeb45f Only get Tmp2 for cases where number of operands is > 1. Fixed return void. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27586 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 06:33:39 +00:00
Chris Lattner
b49e52c7e2 add some todos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27580 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 02:00:08 +00:00
Chris Lattner
f87324e44d Add basic support for legalizing returns of vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27578 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 01:31:51 +00:00
Jim Laskey
1069fbdd2f Use existing information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27574 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-10 23:09:19 +00:00
Evan Cheng
db3c626eb9 Missing break 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27559 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-10 18:54:36 +00:00
Chris Lattner
b22e35a3c3 Add code generator support for VSELECT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-08 22:22:57 +00:00