13842 Commits

Author SHA1 Message Date
Duncan Sands
4e8982a34d The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type of
the input vector, it can be bigger (this is helpful for powerpc where <2 x i16>
is a legal vector type but i16 isn't a legal type, IIRC).  However this wasn't
being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220.
Lightly tweaked version of a patch by Michael Liao.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 09:01:35 +00:00
Evan Cheng
875913439c InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4

to a copy:
r1026 = copy r1024

This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.

rdar://11849816


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 18:55:07 +00:00
Nadav Rotem
4b24bf8da3 Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 11:02:16 +00:00
Benjamin Kramer
a67306d21f Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 09:39:04 +00:00
Nadav Rotem
b6e89f0471 Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 08:52:09 +00:00
Owen Anderson
45299995d6 Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.
This is a speculative fix for a problem on Mips reported by Akira Hatanaka.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 06:38:55 +00:00
Jakob Stoklund Olesen
47730a774d Require and preserve LoopInfo for early if-conversion.
It will surely be needed by heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:39:56 +00:00
Chandler Carruth
4e996de58c Teach the LiveInterval::join function to use the fast merge algorithm,
generalizing its implementation sufficiently to support this value
number scenario as well.

This cuts out another significant performance hit in large functions
(over 10k basic blocks, etc), especially those with "natural" CFG
structures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:25:21 +00:00
Jakob Stoklund Olesen
1f523dc45e Run early if-conversion in domtree post-order.
This ordering allows nested if-conversion without using a work list, and
it makes it possible to update the dominator tree on the fly as well.

Any erased basic blocks will always be dominated by the current
post-order position, so the domtree can be pruned without invalidating
the iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:18:23 +00:00
Chandler Carruth
1b8da1d8f1 Fix a bug where I didn't test for an empty range before inspecting the
back of it.

I don't have anything even remotely close to a test case for this. It
only broke two build bots, both of them doing bootstrap builds, one of
them a dragonegg bootstrap. It doesn't break for me when I bootstrap
either. It doesn't reproduce every time or on many machines during the
bootstrap. Many thanks to Duncan Sands who got the exact command (and
stage of the bootstrap) which failed on the dragonegg bootstrap and
managed to get it to trigger under valgrind with debug symbols. The fix
was then found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 15:41:33 +00:00
Nadav Rotem
2dd83eb1ab Improve the loading of load-anyext vectors by allowing the codegen to load
multiple scalars and insert them into a vector. Next, we shuffle the elements
into the correct places, as before.
Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the
migration of bitcasts happened too late in the SelectionDAG process.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 13:25:08 +00:00
Chandler Carruth
e585e75612 Add an efficient merge operation to LiveInterval and use it to avoid
quadratic behavior when performing pathological merges. Fixes the core
element of PR12652.

There is only one user of addRangeFrom left: join. I'm hoping to
refactor further in a future patch and have join use this merge
operation as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 05:16:17 +00:00
Chandler Carruth
261b633089 Teach LiveIntervals how to verify themselves and start using it in some
of the trick merge routines. This adds a layer of testing that was
necessary when implementing more efficient (and complex) merge logic for
this datastructure.

No functionality changed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 05:06:03 +00:00
Andrew Trick
70cb1778b9 indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 20:43:01 +00:00
Owen Anderson
d9bf71fdd2 Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional move, since there are only two possible values.
Previously, this would become an integer extension operation, followed by a real integer->float conversion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 20:31:12 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 04:00:00 +00:00
Chad Rosier
6016a4a162 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 17:44:22 +00:00
Chad Rosier
fd065bbed1 [fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 17:33:39 +00:00
Alexey Samsonov
b67bd33e8e Fix PR13202 and a regtest.
DwarfDebug class could generate the same (inlined) DIVariable twice:
1) when trying to find abstract debug variable for a concrete inlined instance.
2) when explicitly collecting info for variables that were optimized out.

This change makes sure that this duplication won't happen and makes
Clang pass "gdb.opt/inline-locals" test from gdb testsuite.

Reviewed by Eric Christopher.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 08:45:08 +00:00
Jakob Stoklund Olesen
86fc3100b5 Add some comments suggested in code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 02:31:22 +00:00
Chandler Carruth
95c88b8cb2 Optimize extendIntervalEndTo a tiny bit by saving one call through the
vector erase. No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 12:40:45 +00:00
Chandler Carruth
d862d697d2 Finish fixing the MachineOperand hashing, providing a nice modern
hash_value overload for MachineOperands. This addresses a FIXME
sufficient for me to remove it, and cleans up the code nicely too.

The important changes to the hashing logic:
- TargetFlags are now included in all of the hashes. These were complete
  missed.
- Register operands have their subregisters and whether they are a def
  included in the hash.
- We now actually hash all of the operand types. Previously, many
  operand types were simply *dropped on the floor*. For example:
  - Floating point immediates
  - Large integer immediates (>64-bit)
  - External globals!
  - Register masks
  - Metadata operands
- It removes the offset from the block-address hash; I'm a bit
  suspicious of this, but isIdenticalTo doesn't consider the offset for
  black addresses.

Any patterns involving these entities could have triggered extreme
slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs
you think might be closed now... I'm looking myself, but I may miss
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 11:06:22 +00:00
Duncan Sands
483c54b811 All cases are covered, no need for a default. This deals with the
corresponding clang warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 10:14:33 +00:00
Chandler Carruth
b8087451ca The hash function for MI expressions, used by MachineCSE, is really
broken. This patch fixes the superficial problems which lead to the
intractably slow compile times reported in PR13225.

The specific issue is that we were failing to include the *offset* of
a global variable in the hash code. Oops. This would in turn cause all
MIs which were only distinguishable due to operating on different
offsets of a global variable to produce identical hash functions. In
some of the test cases attached to the PR I saw hash table activity
where there were O(1000) probes-per-lookup *on average*. A very few
entries were responsible for most of these probes.

There is still quite a bit more to do here. The ad-hoc layering of data
in MachineOperands makes them *extremely* brittle to hash correctly.
We're missing quite a few other cases, the only ones I've fixed here are
the specific MO types which were allowed through the assert() in
getOffset().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 10:03:57 +00:00
Duncan Sands
e7de3b29f7 Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1
booleans.  Patch by James Benton.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 09:32:46 +00:00
Nick Lewycky
7a7a6db6d7 Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 06:19:21 +00:00
Jakob Stoklund Olesen
33a537a5c4 Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.

The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.

Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 23:53:23 +00:00
Jakob Stoklund Olesen
9389ec7375 Print SlotIndexes when available for -print-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 23:53:19 +00:00
Jakob Stoklund Olesen
9e51b14faa Allow multiple terminators to read virtual registers.
Find the kill as the last terminator to read SrcReg.

Patch by Philipp Brüschweiler!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 19:52:05 +00:00
Jakob Stoklund Olesen
f86c00f1f8 Make sure -print-machineinstrs applies to the first pass as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 19:28:27 +00:00
Stepan Dyatkovskiy
66d79cefcb Reverted r156659, due to probable performance regressions, DenseMap should be used here:
IntegersSubsetMapping
  - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement
    if possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 05:53:05 +00:00
Eric Christopher
caba263c8e Reduce some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 02:02:18 +00:00
Matt Beaumont-Gay
00f43076a3 Fix some ascii art in a comment to not have trailing backslashes (inspiration
from IfConversion.cc), and fix some spelling and grammar in the surrounding
prose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 01:09:45 +00:00
Jakob Stoklund Olesen
33242fd3ed Add an experimental early if-conversion pass, off by default.
This pass performs if-conversion on SSA form machine code by
speculatively executing both sides of the branch and using a cmov
instruction to select the result. This can help lower the number of
branch mispredictions on architectures like x86 that don't have
predicable instructions.

The current implementation is very aggressive, and causes regressions on
mosts tests. It needs good heuristics that have yet to be implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 00:09:54 +00:00
Stepan Dyatkovskiy
6a59073735 Part of r159527. Splitted into series of patches and gone with fixed PR13256:
IntegersSubsetMapping
  - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement
    if possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03 13:46:45 +00:00
Eric Christopher
c723eb1aef Revert "IntRange:" as it appears to be breaking self hosting.
This reverts commit b2833d9dcba88c6f0520cad760619200adc0442c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 23:22:21 +00:00
Chandler Carruth
6068c48498 All glory to address sanitizer. ;]
It appears to have caught a use-after-free introduced as by r159567
and/or friends which call 'addPass' from many more places. The bug in
'addPass' doesn't appear to be new, and was spotted by inspection when
ASan shown a bright light of a stacktrace at these functions.

Hopefully this will fix the ASan failure -- I have no test case other
than running an ASan-built clang over the test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 22:56:41 +00:00
Evan Cheng
769951f6cc Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 22:39:56 +00:00
Andrew Trick
3d4ed08574 misched: allow NULL InstrItineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 21:55:12 +00:00
Eric Christopher
9eb4f8a3e6 Turn an assert into an error to make it a bit more friendly.
Part of rdar://6880388 and rdar://11766377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159590 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 21:16:43 +00:00
Bob Wilson
30a507a1f5 Extend TargetPassConfig to allow running only a subset of the normal passes.
This is still a work in progress but I believe it is currently good enough
to fix PR13122 "Need unit test driver for codegen IR passes".  For example,
you can run llc with -stop-after=loop-reduce to have it dump out the IR after
running LSR.  Serializing machine-level IR is not yet supported but we have
some patches in progress for that.

The plan is to serialize the IR to a YAML file, containing separate sections
for the LLVM IR, machine-level IR, and whatever other info is needed.  Chad
suggested that we stash the stop-after pass in the YAML file and use that
instead of the start-after option to figure out where to restart the
compilation.  I think that's a great idea, but since it's not implemented yet
I put the -start-after option into this patch for testing purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 19:48:45 +00:00
Bob Wilson
6b2bb15bf7 Move assertion with TargetPassConfig's Initialized flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 19:48:39 +00:00
Bob Wilson
3fb99a7368 Consistently use AnalysisID types in TargetPassConfig.
This makes it possible to just use a zero value to represent "no pass", so
the phony NoPassID global variable is no longer needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 19:48:37 +00:00
Bob Wilson
564fbf6aff Add all codegen passes to the PassManager via TargetPassConfig.
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging.  No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 19:48:31 +00:00
Manman Ren
5f917cd3fa Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtual
register does not have multiple definitions. Modified TwoAddressInstructionPass
to use getUniqueVRegDef instead of getVRegDef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 18:55:36 +00:00
Andrew Trick
218ee74a01 Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 18:10:42 +00:00
Stepan Dyatkovskiy
b2833d9dcb IntRange:
- Changed isSingleNumber method behaviour. Now this flag is calculated on demand.
IntegersSubsetMapping
  - Optimized diff operation.
  - Replaced type of Items field from std::list with std::map.
  - Added new methods:
    bool isOverlapped(self &RHS)
    void add(self& RHS, SuccessorClass *S)
    void detachCase(self& NewMapping, SuccessorClass *Succ)
    void removeCase(SuccessorClass *Succ)
    SuccessorClass *findSuccessor(const IntTy& Val)
    const IntTy* getCaseSingleNumber(SuccessorClass *Succ)
IntegersSubsetTest
  - DiffTest: Added checks for successors.
SimplifyCFG
  Updated SwitchInst usage (now it is case-ragnes compatible) for
    - SimplifyEqualityComparisonWithOnlyPredecessor
    - FoldValueComparisonIntoPredecessors



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 13:02:18 +00:00
Rafael Espindola
9c3d5a70f4 Now that RegistersDefinedFromSameValue handles one instruction being an
implicit_def, the other instruction can be anything, including instructions
that define multiple values. Be careful about that and don't assume what operand
0 is.
Fixes pr13249.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01 17:08:01 +00:00
Rafael Espindola
682e8d05c7 Handle implicit_defs in the register coalescer. I am still trying to produce
a reduced testcase, but this fixes pr13209.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-30 01:45:55 +00:00
Manman Ren
de7266c611 Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare
instructions with two register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29 21:33:59 +00:00