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25489 Commits

Author SHA1 Message Date
Amaury de la Vieuville
46e136c952 ARM: fix CPS decoding when ambiguous with QADD 
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 13:38:52 +00:00
Amaury de la Vieuville
c64835b0c5 ARM: fix VCVT decoding 
UNPRED was reported instead of UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 13:29:11 +00:00
JF Bastien
2c69e90064 Fix unused variable warning from my previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183601 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 00:51:51 +00:00
Akira Hatanaka
7462a875d9 [mips] Use a helper function which compares the size of the source and 
destination operands of an instruction.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 00:14:54 +00:00
Vincent Lejeune
843c6c2d0e R600: Use a refined heuristic to choose when switching clause 
This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)

There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183593 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 23:30:34 +00:00
Vincent Lejeune
b01bdf87ff R600: Anti dep better handled in tex clause 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 23:30:26 +00:00
Jakob Stoklund Olesen
ec2aaad01b Remember the anyext patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183589 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:59:29 +00:00
Jakob Stoklund Olesen
7de1d327f1 Add missing zextloadi1 to i64 patterns. PR16721. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:55:05 +00:00
Hal Finkel
40be73bed7 Disallow i64 div/rem in PPC32 counter loops 
On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:16:19 +00:00
Bill Wendling
e488b4ecdc Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183572 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:04:35 +00:00
Bill Wendling
a5e5ba611f Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:00:34 +00:00
Bill Wendling
1ce4985e01 Remove unused c'tor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183570 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:59:31 +00:00
Tom Stellard
df74b86e1e R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:52:05 +00:00
Bill Wendling
fc61b6f111 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:42:15 +00:00
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:37:48 +00:00
Bill Wendling
c1dcb8d654 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:35:25 +00:00
Bill Wendling
b5632b5b45 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:55 +00:00
Tom Stellard
ce961477be R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:55 +00:00
Tom Stellard
630547ada4 R600: Move Subtarget feature definitions into AMDGPU.td 
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183559 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:49 +00:00
Tom Stellard
6f3b49323c R600: Remove unnecessary include 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183558 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:43 +00:00
JF Bastien
8fc760cbe8 ARM FastISel integer sext/zext improvements 
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:10:37 +00:00
Benjamin Kramer
1983a4cbf1 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183549 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 19:59:34 +00:00
Benjamin Kramer
2e0cebd881 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183541 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:18:12 +00:00
Roman Divacky
6ca5fd3f30 Fix a typo in asm string of BP* family of instructions. With this fix 
I am able to compile/assemble/link/run /bin/echo from FreeBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 17:46:57 +00:00
Benjamin Kramer
47b0c0a9a0 R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183532 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 16:13:49 +00:00
Vincent Lejeune
74f03455e5 R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183528 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 15:44:53 +00:00
Benjamin Kramer
041399aad5 Fold variable that's only used in assert into the assert. 
Avoids unused variable warnings in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 11:23:35 +00:00
Bill Wendling
80ada583f3 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 07:55:53 +00:00
Bill Wendling
41e632d9e1 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 07:04:14 +00:00
Bill Wendling
ed8b5b55a4 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183492 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:30:15 +00:00
Bill Wendling
637eab6a3b Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183491 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:26:43 +00:00
Bill Wendling
54a56fad36 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:19:56 +00:00
Bill Wendling
57148c166a Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 05:54:19 +00:00
Bill Wendling
4393f48c03 Don't cache the instruction info and register info objects. 
These objects are internal to the TargetMachine object and may change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 05:00:11 +00:00
Arnold Schwaighofer
c6752d5565 ARM sched model: Use the right resources for DIV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183477 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 01:16:15 +00:00
Arnold Schwaighofer
873ff29514 ARM sched model: Add VFP div instruction on Swift 
Reapply 183271.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 01:10:36 +00:00
Arnold Schwaighofer
7f155d7d2b ARM sched model: Add SIMD/VFP load/store instructions on Swift 
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183464 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 00:04:28 +00:00
Venkatraman Govindaraju
01021a8b93 [Sparc]: Use cmp instruction instead of subcc to compare integers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 00:03:36 +00:00
Vincent Lejeune
81c5d11c25 R600: Rewrite an awkward loop in R600MachineScheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 23:08:32 +00:00
Arnold Schwaighofer
6b10d85303 Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" 
Breaks linux build bots (I thought the problem was something else).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183447 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 21:08:18 +00:00
Arnold Schwaighofer
5bf5b96c2b ARM sched model: Add SIMD/VFP load/store instructions on Swift 
Reapply 183270.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 21:02:18 +00:00
Arnold Schwaighofer
5be946b486 ARM sched model: Add integer VFP/SIMD instructions on Swift 
Reapply 183269.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 20:26:18 +00:00
Arnold Schwaighofer
d9445b6221 ARM sched model: Add integer load/store instructions on Swift 
Reapply 183268.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183438 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 20:11:56 +00:00
Arnold Schwaighofer
67c2056e00 ARM sched model: Add integer arithmetic instructions on Swift 
Reapply 183267.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183436 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 19:49:46 +00:00
Arnold Schwaighofer
d8f8c35f4d ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

Reapply 183266.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 19:30:21 +00:00
Arnold Schwaighofer
f1f6dcefa8 ARM sched model: Add branch thumb instructions 
Reapply 183265.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:51:01 +00:00
Arnold Schwaighofer
a6db677197 ARM sched model: Add branch thumb2 instructions 
Reapply 183264.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:42:09 +00:00
Arnold Schwaighofer
87aab6dc96 ARM sched model: Add branch instructions 
Reapply 183263.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:21:13 +00:00
Arnold Schwaighofer
3ba4778c95 ARM sched model: Add preload thumb2 instructions 
Reapply 183262.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183427 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:06:30 +00:00
Arnold Schwaighofer
e022a6b0f4 ARM sched model: Add preload instructions 
Reapply 183261.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 17:26:12 +00:00