Commit Graph

5 Commits

Author SHA1 Message Date
Andrea Di Biagio
888cbad774 Fix edge condition in DAGCombiner to improve codegen of shift sequences.
When canonicalizing dags according to the rule
(shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1))

remember to add the new shl dag to the DAGCombiner worklist of nodes.
If we don't explicitly add it to the worklist of nodes to visit, we
may not trigger later on the rule that folds the shift left + logical
shift right into a AND instruction with bitmask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 11:02:58 +00:00
Andrea Di Biagio
4cc117883d Remove superfluous comment accidentally checked-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:13:58 +00:00
Andrea Di Biagio
a9f113d066 Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 11:37:05 +00:00
Andrea Di Biagio
6c73cf5a8a Revert r191393 since it caused pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 16:54:01 +00:00
Andrea Di Biagio
2ce3ac8dd8 Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).

The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.

This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 19:01:01 +00:00