Daniel Sanders
a6c3a4ee76
[mips][msa] Added cfcmsa, and ctcmsa
...
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 10:26:24 +00:00
Daniel Sanders
f00539cc5a
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 10:12:09 +00:00
Daniel Sanders
c9617b9a9d
[mips][msa] Added bitconverts for vector types for big and little-endian
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 09:40:30 +00:00
Daniel Sanders
c73488a38e
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 10:10:13 +00:00
Daniel Sanders
c5158b869b
[mips][msa] Removed fcge, fcgt, fsge, fsgt
...
These instructions were present in a draft spec but were removed before
publication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:41:47 +00:00
Daniel Sanders
6ef333501e
[mips][msa] Added insve
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:22:54 +00:00
Daniel Sanders
c149fbbe27
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:38:21 +00:00
Daniel Sanders
ea549a847d
Reverted test commit (r188556)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188557 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 15:27:12 +00:00
Daniel Sanders
1dbfa36ba1
Test commit. Just a blank line
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188556 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 15:26:36 +00:00
Jack Carter
bd71eea899
[Mips][msa] Added the simple builtins (madd_q to xori)
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Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 14:22:07 +00:00
Jack Carter
d0f99639c1
[Mips][msa] Added the simple builtins (fadd to ftq)
...
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 13:45:36 +00:00
Jack Carter
e2a9376b1b
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
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Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
Jack Carter
3f70e908c3
[Mips][msa] Added initial MSA support.
...
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:54:07 +00:00
