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13861 Commits

Author SHA1 Message Date
Jim Grosbach
53727fc659 Add a couple of FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:35:57 +00:00
Devang Patel
cbfadfc4b3 Fix test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137847 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:48:28 +00:00
Devang Patel
4be7fb0742 Remove superficial test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:39:13 +00:00
Devang Patel
0cd513269f Robustify test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:38:44 +00:00
Owen Anderson
4c81cf5dfc Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:21:36 +00:00
Eli Friedman
447f95202a Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive 
with unknown instructions.

Fixes PR10687.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:10:43 +00:00
Jim Grosbach
358499ea3b Thumb assembly parsing and encoding for ADC(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:55:28 +00:00
Jim Grosbach
b1ee18ee69 Add missing '@' delimiter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:46:01 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes
0e6d230abd Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes
666f500592 Update test to not use the scalar type to splat from a load 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:15 +00:00
Bruno Cardoso Lopes
fc0a702128 Now that we have a canonical way to handle 256-bit splats: 
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137807 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:10 +00:00
Akira Hatanaka
bb15e117d3 Add support for ext and ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:05:42 +00:00
Jim Grosbach
89e2aa6afd Thumb ADD(immediate) parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:57:34 +00:00
Eli Friedman
bfd5040ddc An additional atomic test; related to r137662. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:29:17 +00:00
Jim Grosbach
194bd89829 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:20:01 +00:00
Eli Friedman
054ddf799b A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop 
making random bad assumptions about instructions which are not explicitly listed.  

Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137777 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:06:31 +00:00
Eric Christopher
f213ad1a55 Remove tests that have been obsoleted or migrated to clang/optimizer tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137775 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:46:25 +00:00
Jim Grosbach
3912b73c74 Thumb assembly parsing and encoding for ADD(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:34:08 +00:00
Eli Friedman
1fc291f0d3 Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137755 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:12:35 +00:00
Jim Grosbach
c2408d3ce5 Add testcase for r137746. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:11:21 +00:00
Jim Grosbach
be2ac8ca7b Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:55:41 +00:00
Jim Grosbach
47a0d52b69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:45:50 +00:00
Bruno Cardoso Lopes
3b86598cfa Instead of always leaving the work to the generic legalizer when 
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 18:21:54 +00:00
Akira Hatanaka
a43d3e71ec Add test case for r137711. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137725 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 17:32:01 +00:00
Jim Grosbach
d0d3f7e01f ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 17:06:20 +00:00
Akira Hatanaka
614051a1c5 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 03:51:51 +00:00
Eli Friedman
34fd67c7bc Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 01:42:56 +00:00
Eli Friedman
2199dfb0e6 Revert a bit of r137667; the logic in question can safely handle atomic load/store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 01:28:22 +00:00
Eric Christopher
89a01a0cbd Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and 
FileCheckize. It is more properly an optimizer test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137700 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 01:17:17 +00:00
Eli Friedman
8176388d65 Update SimplifyCFG for atomic operations. 
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:59:28 +00:00
Eli Friedman
fd06b3cfa1 Add comments and test for atomic load/store and mem2reg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:55:52 +00:00
Owen Anderson
a9c989d55a Add a test file for Thumb2 NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes
1deddbbd56 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:36:45 +00:00
Eli Friedman
cc4a0435b7 Update instcombine for atomic load/store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 22:09:40 +00:00
Bruno Cardoso Lopes
50b37c7920 Fix PR10656. It's only profitable to use 128-bit inserts and extracts 
when AVX mode is one. Otherwise is just more work for the type
legalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 21:45:54 +00:00
Owen Anderson
c4bda5633a Add some more comprehensive VFP decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 21:29:01 +00:00
Eric Christopher
801f10f716 Fix this test to avoid leaving a temporary file behind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:55:03 +00:00
Eli Friedman
97671565ff Atomic load/store support in LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137648 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:52:09 +00:00
Owen Anderson
c537f3be0c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:51:32 +00:00
Eric Christopher
f000957aad Add an ipsccp test. Migrated from test/FrontendC++. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137646 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:50:36 +00:00
Owen Anderson
95d01b8898 Add a test for Thumb1 LDRSH decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:15:43 +00:00
Owen Anderson
bd37b721c8 Add testcase for STRH. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:12:03 +00:00
Owen Anderson
5df7ef6cdb Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53 Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 18:44:44 +00:00
Nick Lewycky
28b84ff4ce This transform is not safe. Thanks to Eli for pointing that out! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-14 04:51:49 +00:00
Nick Lewycky
7f0170c197 Don't attempt to add 'nsw' when intermediate instructions had no such guarantee. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-14 03:41:33 +00:00
Nick Lewycky
daf27ea899 Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis 
when combining add and sub instructions. Patch by Pranav Bhandarkar!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-14 01:45:19 +00:00
Eli Friedman
9a0f436da2 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-13 17:06:34 +00:00