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4975 Commits

Author SHA1 Message Date
Cameron Zwarich
53aac15a60 Fix the GCC test suite issue exposed by r127477, which was caused by stack 
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 21:51:56 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 19:30:30 +00:00
Cameron Zwarich
592ca3fda9 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 04:54:27 +00:00
Eric Christopher
de5e101b0d Change the x86 32-bit scheduler to register pressure and fix up the 
corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 01:05:58 +00:00
Evan Cheng
9ef82ce4fe Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 00:48:56 +00:00
Jim Grosbach
d4a16ad85d Properly pseudo-ize MOVCCr and MOVCCs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-10 23:56:09 +00:00
Justin Holewinski
fca9efcbc4 PTX: Add preliminary support for floating-point divide and multiply-and-add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127410 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-10 16:57:18 +00:00
Che-Liang Chiou
2f5565d21c ptx: add the rest of special registers of ISA version 2.0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-10 04:05:57 +00:00
Stuart Hastings
03d5826164 Revert 127359; it broke lencod. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127382 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-10 00:25:53 +00:00
Daniel Dunbar
edfab0ca1e Revert "Re-enable test and hope to silence the buildbots", still broken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 22:48:46 +00:00
Benjamin Kramer
7bff3e7c1b Fix mistyped CHECK lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 22:07:31 +00:00
Stuart Hastings
167831dcac Tweak test to work on Linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 21:35:10 +00:00
Stuart Hastings
2f5443be11 Disable this test temporarily to reduce BuildBot complaints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 21:33:47 +00:00
Stuart Hastings
2f26fa4838 X86 byval copies no longer always_inline. <rdar://problem/8706628> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 21:10:30 +00:00
Bruno Cardoso Lopes
842db07c61 Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 21:05:32 +00:00
Bruno Cardoso Lopes
2c19ed9d67 Re-enable test and hope to silence the buildbots 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127357 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 21:00:16 +00:00
Bruno Cardoso Lopes
557ce71ec9 try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 20:59:05 +00:00
Jakob Stoklund Olesen
5d96e5a1cc Make physreg coalescing independent on the number of uses of the virtual register. 
The damage done by physreg coalescing only depends on the number of instructions
the extended physreg live range covers. This fixes PR9438.

The heuristic is still luck-based, and physreg coalescing really should be
disabled completely. We need a register allocator with better hinting support
before that is possible.

Convert a test to FileCheck and force spilling by inserting an extra call. The
previous spilling behavior was dependent on misguided physreg coalescing
decisions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 19:27:06 +00:00
Jakob Stoklund Olesen
dda386c44d Delete a test case that is very sensitive to coalescer behavior. 
The test is derived from an old miscompilation of
MultiSource/Benchmarks/VersaBench/8b10b which is run regularly, so we are not
losing coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127350 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 19:27:02 +00:00
Bruno Cardoso Lopes
954dac0f88 Improve varags handling, with testcases. Patch by Sasa Stankovic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 19:22:22 +00:00
Andrew Trick
5d332e0c3e This test case should work with list-ilp or list-burr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 19:17:10 +00:00
NAKAMURA Takumi
3ca99435e9 Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 11:33:15 +00:00
Eric Christopher
e11128dd9d Fix testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 00:41:41 +00:00
Benjamin Kramer
e5ef311ee3 Strip cruft. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 20:19:10 +00:00
Eric Christopher
2b24e7f3df Add a testcase for r127263. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 19:49:15 +00:00
Benjamin Kramer
c175a4bd7e X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1. 
Found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 15:20:20 +00:00
Justin Holewinski
c6f24f4086 PTX: Add intrinsic support for ntid, ctaid, and nctaid registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 14:10:18 +00:00
Eric Christopher
7c2cdb1c05 Turn on list-ilp scheduling by default on x86 and x86-64, fix up 
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.

Performance results:

roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated

john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES

Small compile time impact.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 02:42:25 +00:00
Bob Wilson
79f56c9618 Fix a compiler crash where a Glue value had multiple uses. Radar 9049552. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 01:17:20 +00:00
Che-Liang Chiou
0df2c50c2b ptx: add basic intrinsic support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 14:17:37 +00:00
NAKAMURA Takumi
89be0acecf test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 02:38:02 +00:00
Bruno Cardoso Lopes
38b5e86b9c Improve div/rem node handling on mips. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
650af5d0f8 Add testcase for r127032 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:48:39 +00:00
Dan Gohman
a7a841adb8 When decling to reuse existing expressions that involve casts, ignore 
bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:46:46 +00:00
Joerg Sonnenberger
89e0f386f3 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:03:14 +00:00
Bruno Cardoso Lopes
ca8a2aa921 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:01:52 +00:00
Devang Patel
c8888c7d80 XFAIL for all. These tests are darwin specific anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:38:10 +00:00
Devang Patel
53dc40a45f Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:11:05 +00:00
Kalle Raiskila
31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
7f5de8b4c6 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 12:00:11 +00:00
Eli Friedman
81c5ef8649 Revert r123908; the code in question is completely untested and wrong. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:33:23 +00:00
Joerg Sonnenberger
ea83b13350 Bug#9033: For the ELF assembler output, always quote the section name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:31:08 +00:00
Stuart Hastings
44456e86c8 Test case for r126864. Radar 9056407. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:41:40 +00:00
David Greene
a20244d1ba [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 17:23:43 +00:00
Cameron Zwarich
56e3793acf Eliminate the unused CodeGenPrepare option to split critical edges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:31:46 +00:00
Che-Liang Chiou
fd8978b021 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:20:28 +00:00
Dan Gohman
0cbe91ba3b Don't re-use existing addrec expansions if they contain casts. 
This fixes PR9259.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:34:10 +00:00
Evan Cheng
f06e6c2ba7 Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:08:17 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Jakob Stoklund Olesen
bafd516d3e Fix typo introduced by r126661: "Fix a typo which ..." 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 19:18:59 +00:00