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71 Commits

Author SHA1 Message Date
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Owen Anderson
438f68df35 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:23 +00:00
Owen Anderson
cf6039548b Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 22:45:43 +00:00
Owen Anderson
5f801ba6ef The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 20:06:49 +00:00
Owen Anderson
7f76baed5e Enhance the fixed length disassembler to better handle operand decoding failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 18:44:37 +00:00
Owen Anderson
eb809f562e Correctly handle scattered operands where the bits of the operand are contiguous, but out of order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 23:01:18 +00:00
David Greene
05bce0beee Unconstify Inits 
Remove const qualifiers from Init references, per Chris' request.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 22:43:06 +00:00
David Greene
f37dd02f77 [AVX] Constify Inits 
Make references to Inits const everywhere.  This is the final step
before making them unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 19:07:05 +00:00
Owen Anderson
ea2429896a Third time's the charm for implementing tied operand decoding properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136478 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 18:28:52 +00:00
Owen Anderson
d217da1131 Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:32:03 +00:00
Owen Anderson
00ef6e3a30 Enhance the fixed-length decoder emitter to support tied operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 23:56:20 +00:00
Owen Anderson
d1e38dfb8d Enhance the fixed-length decoder emitter to support parsing scattered fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 21:54:31 +00:00
Owen Anderson
f1a0090073 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:06:00 +00:00
Eric Christopher
d568b3f552 Revert r134921, 134917, 134908 and 134907. They're causing failures 
in multiple buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 23:06:52 +00:00
David Greene
d4a9066c93 [AVX] Make Inits Foldable 
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 18:25:51 +00:00
Jim Grosbach
806fcc040e Don't require pseudo-instructions to carry encoding information. 
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 21:33:38 +00:00
Owen Anderson
bea6f615ee Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. 
Patch by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 21:06:21 +00:00
Owen Anderson
57557155c9 Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-18 18:42:26 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Owen Anderson
4dd27ebcc2 Ignore isCodeGenOnly instructions when generating diassembly tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-14 20:58:49 +00:00
Owen Anderson
d8c87888a7 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings. 
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-18 21:51:29 +00:00