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22422 Commits

Author SHA1 Message Date
Jim Grosbach
55499db9a0 ARM: Tidy up. Remove unused template parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161222 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 22:08:27 +00:00
Jim Grosbach
9249ef3b99 ARM: More InstAlias refactors to use #NAME#. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161220 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 21:59:52 +00:00
Jim Grosbach
5c6c128b81 ARM: Refactor instaliases using TableGen support for #NAME#. 
Now that TableGen supports references to NAME w/o it being explicitly
referenced in the definition's own name, use that to simplify
assembly InstAlias definitions in multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 21:50:41 +00:00
Manman Ren
127eea87d6 X86 Peephole: fold loads to the source register operand if possible. 
Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 19:37:32 +00:00
Akira Hatanaka
af26626067 Move the code that creates instances of MipsInstrInfo and MipsFrameLowering out 
of MipsTargetMachine.cpp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 18:21:47 +00:00
Akira Hatanaka
bddf83614a Set transient stack alignment in constructor of MipsFrameLowering and re-enable 
test o32_cc_vararg.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161189 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 18:15:13 +00:00
Jiangning Liu
1c37814960 Support fpv4 for ARM Cortex-M4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:35:55 +00:00
Jiangning Liu
fd652df8b3 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:29:50 +00:00
Jiangning Liu
c1b7ca5ba2 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:21:27 +00:00
Jiangning Liu
1fb27eccf5 Fix #13241, a bug around shift immediate operand for ARM instruction ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:13:13 +00:00
Manman Ren
d7d003c2b7 X86 Peephole: fold loads to the source register operand if possible. 
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

This patch is a rework of r160919 and was tested on clang self-host on my local
machine.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 00:56:42 +00:00
Manman Ren
5641424a6c X86: mark GATHER instructios as mayLoad 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 23:28:59 +00:00
Jim Grosbach
cc5fc665e3 ARM: Remove redundant instalias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 20:33:05 +00:00
Jim Grosbach
046eea5247 Clean up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161133 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 20:33:02 +00:00
Jim Grosbach
2769028ab4 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161132 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 20:33:00 +00:00
Chad Rosier
a20e1e7ef5 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 18:39:17 +00:00
Elena Demikhovsky
1503aba4a0 Added FMA functionality to X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 12:06:00 +00:00
Craig Topper
5a2c607153 Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 07:39:18 +00:00
Akira Hatanaka
c15ad85177 Implement MipsJITInfo::replaceMachineCodeForFunction. 
No new test case is added.
This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips
platform.

Patch by Petar Jovanovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161098 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 02:29:24 +00:00
Akira Hatanaka
fa566d02cc Remove unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 00:37:53 +00:00
Akira Hatanaka
71746220d3 Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits 
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 23:52:55 +00:00
Akira Hatanaka
8589010e3d Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and 
MipsSERegisterInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 23:41:32 +00:00
Akira Hatanaka
cdb3ba71ce Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and 
MipsSEFrameLowering.

Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be
reserved if there is a call with a large call frame or there are variable sized
objects on the stack.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 22:50:19 +00:00
Akira Hatanaka
d5cfc0172c Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161083 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 22:11:05 +00:00
Akira Hatanaka
0bc1adbbc4 Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16), 
and MipsSEInstrInfo (for mips32/64).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 21:49:49 +00:00
Akira Hatanaka
b4f921b1f0 Delete mips64 target machine classes. mips target machines can be used in place 
of them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 21:39:17 +00:00
Akira Hatanaka
1d53f1bbab Let PEI::calculateFrameObjectOffsets compute the final stack size rather than 
computing it in MipsFrameLowering::emitPrologue.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 21:28:49 +00:00
Akira Hatanaka
1d165f1c25 Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering. 
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 20:54:48 +00:00
Akira Hatanaka
603f69dc2c Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether 
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161071 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 19:13:07 +00:00
Akira Hatanaka
c4388d4199 Change name of class MipsInst to InstSE to distinguish it from mips16's 
instruction class. SE stands for standard encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161069 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 18:55:01 +00:00
Akira Hatanaka
e2d529ac11 When store nodes or memcpy nodes are created to copy the function call 
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 18:46:41 +00:00
Chad Rosier
d97f3a5ab0 [x86 frame lowering] In 32-bit mode, use ESI as the base pointer. 
Previously, we were using EBX, but PIC requires the GOT to be in EBX before 
function calls via PLT GOT pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 18:29:21 +00:00
Akira Hatanaka
36bcc11236 Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as 
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 18:16:49 +00:00
Craig Topper
c60685e320 Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161029 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 05:18:26 +00:00
Craig Topper
a40476f9cc Tidy up trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 04:58:05 +00:00
Craig Topper
5592b4567d Tidy up trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161026 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-31 04:38:27 +00:00
Kevin Enderby
5af4de18ef Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cpp 
where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.

rdar://10038370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160978 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 18:46:15 +00:00
Craig Topper
818f609459 Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160953 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 07:14:07 +00:00
Craig Topper
49d86c9eb9 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 06:48:11 +00:00
Craig Topper
706698e0b7 Give VCVTTPD2DQ priority over CVTTPD2DQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160942 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:20:32 +00:00
Craig Topper
80e13a5506 Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:14:02 +00:00
Craig Topper
3ff91c3ac6 Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160939 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 01:38:57 +00:00
Craig Topper
19006bdee1 Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 23:26:34 +00:00
Craig Topper
26a79b7b94 Move more SSE/AVX convert instruction patterns into their definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 22:30:06 +00:00
Manman Ren
e8b4a4a9d1 Revert r160920 and r160919 due to dragonegg and clang selfhost failure 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 02:44:09 +00:00
Craig Topper
7fe1b96ef0 Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:59:19 +00:00
Craig Topper
eb6d794834 Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160921 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:36:39 +00:00
Manman Ren
0eb3edea9c X86 Peephole: fold loads to the source register operand if possible. 
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 16:48:01 +00:00
Craig Topper
cdfbcdeeed Make CVTSS2SI instruction definition consistent with CVTSD2SI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 08:28:23 +00:00
Craig Topper
e96d11c833 Fix up memory load types for SSE scalar convert intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160913 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 07:59:59 +00:00