6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-30 16:17:05 +00:00
Code Issues Projects Releases Wiki Activity
87,074 Commits 39 Branches 0 Tags
596e474101ea9a8ecac9d8ee090d31469dbcc61d
Commit Graph

393 Commits

Author SHA1 Message Date
Kevin Enderby
445ba85b8d Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target 
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-29 23:27:20 +00:00
Kevin Enderby
88d12663ab Fix a bug where a 32-bit address with the high bit does not get symbolicated 
because the value is incorrectly being signed extended when passed to
SymbolLookUp().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166234 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-18 21:49:18 +00:00
Tim Northover
93c7c449a1 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 11:18:12 +00:00
Tim Northover
24b9f258f1 Diagnose invalid alignments on duplicating VLDn instructions. 
Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 15:27:12 +00:00
Tim Northover
eae1d34029 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. 
Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 15:17:49 +00:00
Richard Smith
1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM. 
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 23:29:28 +00:00
Craig Topper
960fb74370 Remove unnecessary include of ARMGenInstrInfo.inc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-17 06:21:09 +00:00
Jim Grosbach
fc1a161d76 Switch the fixed-length disassembler to be table-driven. 
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-14 19:06:05 +00:00
Jiangning Liu
fd652df8b3 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:29:50 +00:00
Jiangning Liu
c1b7ca5ba2 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-02 08:21:27 +00:00
Sylvestre Ledru
c8e41c5917 Fix a typo (the the => the) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-23 08:51:15 +00:00
Richard Barton
fae96f17b4 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-10 12:51:09 +00:00
Chad Rosier
270e3625b2 Revert r159938 (and r159945) to appease the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 20:43:34 +00:00
Richard Barton
83cfff6229 Oops - correct broken disassembly for VMOV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 18:20:02 +00:00
Richard Barton
2e7e34ba54 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 16:41:33 +00:00
Richard Barton
c8f2fcc9a3 Correct decoder for T1 conditional B encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 09:12:53 +00:00
NAKAMURA Takumi
dd051a0414 ARMDisassembler.cpp: Fix utf8 char in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-22 21:47:02 +00:00
Kevin Enderby
3610a15c35 Tweak to the fix in r156212, as with the change in removing the shift the 
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:09:52 +00:00
Kevin Enderby
ce734d5ffe Fix a bug in the ARM disassembler for wide branch conditional instructions 
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 22:02:27 +00:00
Kevin Enderby
2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits 
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 22:41:56 +00:00
Silviu Baranga
b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:38:40 +00:00
Jim Grosbach
bb32f1d545 ARM: Tweak tADDrSP definition for consistent operand order. 
Make the operand order of the instruction match that of the asm syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 23:51:33 +00:00
Richard Barton
4d2f077df1 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 08:42:59 +00:00
Richard Barton
f4478f99dd Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 11:13:20 +00:00
Silviu Baranga
35ee7d28a6 Added support for disassembling unpredictable swp/swpb ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 14:18:57 +00:00
Silviu Baranga
fa1ebc6abe Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 13:12:50 +00:00
Kevin Enderby
c5a2a33938 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 00:49:27 +00:00
Kevin Enderby
2a7d3a9373 Fix a few more places in the ARM disassembler so that branches get 
symbolic operands added when using the C disassembler API.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 23:13:34 +00:00
Kevin Enderby
b318cc16c9 Fixed a case of ARM disassembly getting an assert on a bad encoding 
of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:40:17 +00:00
Kevin Enderby
a69da35c12 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:25:40 +00:00
Dylan Noblesmith
75e3b7fb8f ARMDisassembler: drop bogus dependency on ARMCodeGen 
And indirectly, a dependency on most of the core LLVM optimization
libraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 15:48:14 +00:00
Craig Topper
c89c744b69 Remove unnecessary llvm:: qualifications 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-27 07:21:54 +00:00
Silviu Baranga
6fe310e155 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 14:14:49 +00:00
Silviu Baranga
b7c2ed6664 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 13:24:43 +00:00
Kevin Enderby
f0586f08df Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-21 20:54:32 +00:00
Silviu Baranga
5c062ad926 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 15:54:56 +00:00
Craig Topper
b78ca42384 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:16:55 +00:00
Jim Grosbach
ff3164a189 Tidy up. Remove dead code that slipped into previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:52:39 +00:00
Jim Grosbach
4d0983a4d7 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 23:10:38 +00:00
Jim Grosbach
c0fc450f07 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 22:01:44 +00:00
Kevin Enderby
158c8a49c2 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:33:12 +00:00
Jim Grosbach
c3384c93c0 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 21:43:40 +00:00
Jim Grosbach
28f08c93e7 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 19:33:30 +00:00
Derek Schuff
adef06a714 Make MemoryObject accessor members const again 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-29 01:09:06 +00:00
Kevin Enderby
0943303d31 Fix the symbolic operand added for the C disassmbler API for the ARM bl 
thumb instruction.  The PC adjustment is +4 in Thumb mode and +8 in ARM mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 18:15:15 +00:00
Kevin Enderby
b80d571ea8 Updated the llvm-mc disassembler C API to support for the X86 target. 
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-23 18:18:17 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Benjamin Kramer
88b6fc06db Make the EDis tables const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 14:51:07 +00:00
Craig Topper
bc2198133a Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 02:50:20 +00:00
Derek Schuff
2ea93875b2 Enable streaming of bitcode 
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 22:30:29 +00:00