Commit Graph

3990 Commits

Author SHA1 Message Date
Colin LeMahieu
504c77f9c8 [Hexagon] Adding tstbit/bitclr/bitset instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 21:28:58 +00:00
Colin LeMahieu
18f28b2de6 [Hexagon] Adding bit count and twiddling instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:57:56 +00:00
Colin LeMahieu
50b3134fb4 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 20:40:23 +00:00
Ahmed Bougacha
3ddc32292d [MC] Reset the MCInst in the matcher function before adding opcode/operands.
On X86, the Intel asm parser tries to match all memory operand sizes when
none is explicitly specified.  For LEA, which doesn't really have a memory
operand (just a pointer one), this results in multiple successful matches,
one for each memory size.  There's no error because it's same opcode, so
really, it's just one match.  However, the tablegen'd matcher function
adds opcode/operands to the passed MCInst, and this results in multiple
duplicated operands.

This commit clears the MCInst in the tablegen'd matcher function.
We sometimes clear it when the match failed, so there's no expectation of
keeping the previous content anyway.

Differential Revision: http://reviews.llvm.org/D6670


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 18:05:28 +00:00
Colin LeMahieu
e4aafdf6a1 [Hexagon] Adding absolute value, and negate with saturation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 17:44:49 +00:00
Colin LeMahieu
d69e4e2945 [Hexagon] Adding saturate and swizzle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 16:27:17 +00:00
Zoran Jovanovic
78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 14:59:10 +00:00
Vladimir Medic
9e8621e99a Add disassembler tests for mips4 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224335 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 13:02:25 +00:00
Saleem Abdulrasool
fbdea180c0 ARM: diagnose deprecated syntax
The use of SP and PC in the register list for stores is deprecated on ARM
(ARM ARM A.8.8.199):

  ARM deprecates the use of ARM instructions that include the SP or the PC in
  the list.

Provide a deprecation warning from the assembler in the case that the syntax is
ever seen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224319 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 05:53:25 +00:00
Colin LeMahieu
3a0f6b52db [Hexagon] Adding doubleword multiplies with and without accumulation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224293 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 00:07:24 +00:00
Colin LeMahieu
b4838f6d59 [Hexagon] Adding halfword to doubleword multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224289 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 23:29:37 +00:00
Colin LeMahieu
1240508dda [Hexagon] Adding logical-logical accumulation instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 23:19:07 +00:00
Colin LeMahieu
5f702749c1 [Hexagon] Adding a number of additional multiply forms with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 22:10:37 +00:00
Colin LeMahieu
1eb5ad1ecd [Hexagon] Adding misc multiply encodings and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224273 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 21:17:03 +00:00
Colin LeMahieu
8e7359d3a7 [Hexagon] Adding doubleworld accumulating multiplies of halfwords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224267 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 20:17:46 +00:00
Colin LeMahieu
f8396b83c6 [Hexagon] Adding accumulating half word multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224266 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 20:10:28 +00:00
Colin LeMahieu
c3449d705b [Hexagon] Adding multiply with rnd/sat/rndsat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224265 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 20:01:59 +00:00
Ahmed Bougacha
839ff70c7e [X86] And also test INSERTPS shuffle mask pretty-printing.
For r224260.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224264 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 19:47:35 +00:00
Colin LeMahieu
e9e8f1fe77 [Hexagon] Adding encoding bits for halfword multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224261 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 19:22:07 +00:00
Duncan P. N. Exon Smith
1ef70ff39b IR: Make metadata typeless in assembly
Now that `Metadata` is typeless, reflect that in the assembly.  These
are the matching assembly changes for the metadata/value split in
r223802.

  - Only use the `metadata` type when referencing metadata from a call
    intrinsic -- i.e., only when it's used as a `Value`.

  - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode`
    when referencing it from call intrinsics.

So, assembly like this:

    define @foo(i32 %v) {
      call void @llvm.foo(metadata !{i32 %v}, metadata !0)
      call void @llvm.foo(metadata !{i32 7}, metadata !0)
      call void @llvm.foo(metadata !1, metadata !0)
      call void @llvm.foo(metadata !3, metadata !0)
      call void @llvm.foo(metadata !{metadata !3}, metadata !0)
      ret void, !bar !2
    }
    !0 = metadata !{metadata !2}
    !1 = metadata !{i32* @global}
    !2 = metadata !{metadata !3}
    !3 = metadata !{}

turns into this:

    define @foo(i32 %v) {
      call void @llvm.foo(metadata i32 %v, metadata !0)
      call void @llvm.foo(metadata i32 7, metadata !0)
      call void @llvm.foo(metadata i32* @global, metadata !0)
      call void @llvm.foo(metadata !3, metadata !0)
      call void @llvm.foo(metadata !{!3}, metadata !0)
      ret void, !bar !2
    }
    !0 = !{!2}
    !1 = !{i32* @global}
    !2 = !{!3}
    !3 = !{}

I wrote an upgrade script that handled almost all of the tests in llvm
and many of the tests in cfe (even handling many `CHECK` lines).  I've
attached it (or will attach it in a moment if you're speedy) to PR21532
to help everyone update their out-of-tree testcases.

This is part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224257 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 19:07:53 +00:00
Reid Kleckner
2a59b5ed2d Move mips1 tests to test/MC/Disassembler/Mips/mips1
This matches the pattern of the mips2 and 3 tests, as well as our normal
conventions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 17:56:02 +00:00
Vladimir Medic
77b6849e61 Add disassembler tests for mips3 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 16:19:34 +00:00
Vladimir Medic
7dfda5887e Add disassembler tests for mips2 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224252 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 15:58:20 +00:00
Vladimir Medic
6fe13a4f08 This is the first in a series of patches that add missing disassembler tests for mips platform. The patches are divided per version of mips CPU to keep the patches smaller and ease the review. There are no functional changes, code is changed only if new tests reveal a bug.This patch adds disassembler tests for mips1 CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224251 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 15:22:33 +00:00
Colin LeMahieu
5271cab7c9 [Hexagon] Adding double word add/min/minu/max/maxu instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224153 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-12 21:29:25 +00:00
Colin LeMahieu
365cfbc3f0 [Hexagon] Adding J class call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224150 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-12 21:12:27 +00:00
Colin LeMahieu
015408c6b1 [Hexagon] Adding encoding information for sign extend word instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 16:43:06 +00:00
Duncan P. N. Exon Smith
8f616165e4 IR: Canonicalize metadata formatting, NFC
Canonicalize formatting of metadata to make it easier to upgrade via
scripts -- in particular, one line per metadata definition makes it more
`sed`-able.

This is preparation for changing the assembly syntax for metadata [1].

[1]: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141208/248449.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224002 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 06:32:29 +00:00
Colin LeMahieu
b1fac191b2 [Hexagon] Adding combine ri/ir instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-10 22:23:07 +00:00
Colin LeMahieu
f6492bc6b2 [Hexagon] Adding encodings for JR class instructions. Updating complier usages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223967 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-10 21:24:10 +00:00
Colin LeMahieu
9f3b3bca89 [Hexagon] Adding JR class predicated call reg instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223933 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-10 18:24:16 +00:00
Colin LeMahieu
11fa90091b [Hexagon] Fixing broken tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223823 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 20:36:53 +00:00
Colin LeMahieu
20856353b8 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 20:23:30 +00:00
Colin LeMahieu
260731d108 [Hexagon] Adding word combine dot-new form and replacing old combine opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 19:23:45 +00:00
Colin LeMahieu
60d733acc5 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223800 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 18:16:49 +00:00
Robert Khasanov
c50f9f15f5 [AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpose Register) encodings for AVX512-BW/VL subsets
Added encoding tests.
        


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 16:38:41 +00:00
Asiri Rathnayake
838ec33e0c Fix modified immediate bug reported by MC Hammer.
Instructions of the form [ADD Rd, pc, #imm] are manually aliased
in processInstruction() to use ADR. To accomodate this, mod_imm handling
had to be tweaked a bit. Turns out it was the manual aliasing that must
be tweaked to accommodate mod_imms instead. More information about the
parsed instruction is available at the point where processInstruction()
is invoked, which makes it easier to detect a mod_imm at that point rather
than trying to detect a potential alias when a mod_imm is being prepped.
Added a test case and fixed some white spaces as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 13:14:58 +00:00
Colin LeMahieu
73ed2dcdac [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 23:07:59 +00:00
Colin LeMahieu
7ec769c971 [Hexagon] Fixing broken test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223704 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 22:29:06 +00:00
Colin LeMahieu
27fbb34173 [Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223702 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 22:19:14 +00:00
Colin LeMahieu
9804956609 [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223701 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 21:56:47 +00:00
Colin LeMahieu
7b9be18636 [Hexagon] Adding xtype parity, min, minu, max, maxu instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223693 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 21:19:18 +00:00
Colin LeMahieu
a321bd4f19 [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 20:33:01 +00:00
Colin LeMahieu
4772502317 [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 18:33:49 +00:00
Bruno Cardoso Lopes
43edafcc07 [CompactUnwind] Fix register encoding logic
Fix a compact unwind encoding logic bug which would try to encode
more callee saved registers than it should, leading to early bail out
in the encoding logic and abusive use of DWARF frame mode unnecessarily.

Also remove no-compact-unwind.ll which was testing the wrong thing
based on this bug and move it to valid 'compact unwind' tests. Added
other few more tests too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 18:18:32 +00:00
Colin LeMahieu
cf2daa3671 [Hexagon] Adding combine reg, reg with predicated forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 17:33:06 +00:00
Colin LeMahieu
5c7adadf6d [Hexagon] Adding packhl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 17:01:18 +00:00
Colin LeMahieu
ec51bc6f3a [Hexagon] Adding sub/and/or reg, imm forms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:38:29 +00:00
Colin LeMahieu
5db47f1376 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:09:27 +00:00
Colin LeMahieu
4fda99f866 [Hexagon] Adding tfrih/l instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223506 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:07:19 +00:00