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25099 Commits

Author SHA1 Message Date
Arnold Schwaighofer
5bf5b96c2b ARM sched model: Add SIMD/VFP load/store instructions on Swift 
Reapply 183270.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 21:02:18 +00:00
Arnold Schwaighofer
5be946b486 ARM sched model: Add integer VFP/SIMD instructions on Swift 
Reapply 183269.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 20:26:18 +00:00
Arnold Schwaighofer
d9445b6221 ARM sched model: Add integer load/store instructions on Swift 
Reapply 183268.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183438 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 20:11:56 +00:00
Arnold Schwaighofer
67c2056e00 ARM sched model: Add integer arithmetic instructions on Swift 
Reapply 183267.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183436 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 19:49:46 +00:00
Arnold Schwaighofer
d8f8c35f4d ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

Reapply 183266.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 19:30:21 +00:00
Arnold Schwaighofer
f1f6dcefa8 ARM sched model: Add branch thumb instructions 
Reapply 183265.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:51:01 +00:00
Arnold Schwaighofer
a6db677197 ARM sched model: Add branch thumb2 instructions 
Reapply 183264.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:42:09 +00:00
Arnold Schwaighofer
87aab6dc96 ARM sched model: Add branch instructions 
Reapply 183263.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:21:13 +00:00
Arnold Schwaighofer
3ba4778c95 ARM sched model: Add preload thumb2 instructions 
Reapply 183262.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183427 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 18:06:30 +00:00
Arnold Schwaighofer
e022a6b0f4 ARM sched model: Add preload instructions 
Reapply 183261.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 17:26:12 +00:00
Arnold Schwaighofer
f2988a0084 ARM sched model: Add more ALU and CMP thumb instructions 
Reapply of 183260.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183423 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 17:03:13 +00:00
Arnold Schwaighofer
826de688b0 ARM sched model: Add more ALU and CMP thumb2 instructions 
Reapply of 183259.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 16:35:25 +00:00
Vincent Lejeune
5f035d048e R600: Remove leftover code in R600MachineScheduler.cpp 
Spotted by Benjamin Kramer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183413 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 14:18:29 +00:00
Bill Wendling
2ed7659b88 Cast to the correct type. Pointer, not reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183385 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 05:39:29 +00:00
NAKAMURA Takumi
0ac857462f R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] 
FIXME: Is it false alarm?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183371 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7b6d32a361 R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183370 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3ebcf388cd Trailing linefeed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183369 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 02:15:00 +00:00
Bill Wendling
b88cef5a16 Cast to the proper type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183365 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 01:04:21 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:43:09 +00:00
Tom Stellard
c170230b3a R600: Replace predicate loop with predicate function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 23:39:50 +00:00
Vincent Lejeune
f3d6e32c09 R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 21:38:04 +00:00
Vincent Lejeune
512119770e R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 20:27:35 +00:00
Akira Hatanaka
8270e68c56 [mips] brcond + setgt/setugt instruction selection patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 19:49:55 +00:00
Michael Liao
9a508ef64a [PATCH] Fix VGATHER* operand constraints 
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 18:12:26 +00:00
Arnold Schwaighofer
31588f3005 ARM sched model: Add more ALU and CMP instructions 
Reapply of 183258.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 16:36:51 +00:00
Arnold Schwaighofer
c82157378e ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 16:06:11 +00:00
Arnold Schwaighofer
d87bd5627e ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183314 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 14:59:36 +00:00
Mihai Popa
2248cf5906 This is a simple patch that changes RRX and RRXS to accept all registers as operands. 
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 13:23:51 +00:00
Tom Stellard
ad7ecc65b1 R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 03:43:06 +00:00
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols. 
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:33:53 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e Cortex-R5 can issue Thumb2 integer division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
f500aa0b24 ARM sched model: Add VFP div instruction on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:08 +00:00
Arnold Schwaighofer
858f6f8899 ARM sched model: Add SIMD/VFP load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:07 +00:00
Arnold Schwaighofer
e52041c16e ARM sched model: Add integer VFP/SIMD instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:05 +00:00
Arnold Schwaighofer
f3a2329d33 ARM sched model: Add integer load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:04 +00:00
Arnold Schwaighofer
755d1295a5 ARM sched model: Add integer arithmetic instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:02 +00:00
Arnold Schwaighofer
eb9948e781 ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:00 +00:00
Arnold Schwaighofer
002faf20a7 ARM sched model: Add branch thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:59 +00:00
Arnold Schwaighofer
16d915018b ARM sched model: Add branch thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:57 +00:00
Arnold Schwaighofer
36ea791280 ARM sched model: Add branch instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:56 +00:00
Arnold Schwaighofer
fdbca2faac ARM sched model: Add preload thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:54 +00:00
Arnold Schwaighofer
d3b8445d14 ARM sched model: Add preload instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:52 +00:00
Arnold Schwaighofer
23cb39a3d9 ARM sched model: Add more ALU and CMP thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:51 +00:00
Arnold Schwaighofer
1942e3254d ARM sched model: Add more ALU and CMP thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:49 +00:00
Arnold Schwaighofer
4c53731e5b ARM sched model: Add more ALU and CMP instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:47 +00:00
Arnold Schwaighofer
611c6e1359 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:46 +00:00