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110 Commits

Author SHA1 Message Date
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:09:54 +00:00
Evan Cheng
774bc882fd - Do away with SimpleHazardRecognizer.h. It's not used and offers little value. 
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 21:06:53 +00:00
Evan Cheng
729aab3dd3 Allow target to provide its own hazard recognizer to post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 00:12:18 +00:00
Evan Cheng
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:53:24 +00:00
Jim Grosbach
76526f8863 Remove dbg_value workaround and associated command line option 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:34:01 +00:00
Jim Grosbach
de70b1f9be Enable preserving debug information through post-RA scheduling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 22:57:47 +00:00
Jim Grosbach
9001303a3f 80 column and trailing whitespace cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:19:48 +00:00
Jim Grosbach
5468e0928b add cmd line option to leave dbgvalues in during post-RA sceduling. Useful 
while debugging what's mishandled about them in the post-RA pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103805 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:18:04 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Bob Wilson
8295d4c96c As a temporary workaround for post-RA not handling DebugValue instructions, 
just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 00:49:11 +00:00
Dan Gohman
8b3d6682a4 Remove a #include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-12 16:26:03 +00:00
Dale Johannesen
b0812f114b Fix some more places where dbg_value affected codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-05 00:02:59 +00:00
David Greene
e1b2129471 Change errs() to dbgs(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 01:26:01 +00:00
David Goodwin
990d285765 <rdar://problem/7453528>. Track only physical registers that are valid for the target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90970 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 17:18:22 +00:00
Jakob Stoklund Olesen
15d75d9f11 Don't hang on to pointers or references after vector::push_back. 
The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-03 01:49:56 +00:00
David Goodwin
557bbe6b5d Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 19:32:48 +00:00
David Goodwin
87d21b92fc Allow target to specify regclass for which antideps will only be broken along the critical path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 19:52:48 +00:00
David Goodwin
12dd99dc30 Rename registers to break output dependencies in addition to anti-dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87015 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 19:08:21 +00:00
David Goodwin
c2e8a7e8d2 Fixed to address code review. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:15:47 +00:00
David Goodwin
54097836f3 Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 01:19:35 +00:00
David Goodwin
4de099d8ca Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 20:57:50 +00:00
Dan Gohman
0ba90f3e34 Make -print-machineinstrs more readable. 
- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85682 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 20:19:03 +00:00
David Goodwin
82c7248518 Make AntiDepReg.h internal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85412 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:29:54 +00:00
David Goodwin
e10deca33e Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85166 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:31:16 +00:00
David Goodwin
ada0ef86d9 Define virtual destructor in *.cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 19:41:00 +00:00
David Goodwin
348777110a Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 19:32:42 +00:00
David Goodwin
2e7be612d5 Break anti-dependence breaking out into its own class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 16:59:04 +00:00
Nick Lewycky
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:33:48 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 23:19:17 +00:00
Dan Gohman
c1ae8c9b8f Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 01:44:44 +00:00
David Goodwin
7441d14873 Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 22:50:43 +00:00
David Goodwin
480c529e02 Checkpoint more aggressive anti-dependency breaking for post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84658 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 19:54:44 +00:00
Evan Cheng
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 21:06:15 +00:00
Evan Cheng
c83da2f9e3 If post-alloc scheduler is not enabled, it should return false, not true. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84248 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:10:34 +00:00
David Goodwin
d452ea6a64 Add debugging output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 19:16:03 +00:00
Dan Gohman
5bf7c2a346 Fix a missing initialization of PostRAScheduler's AA member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83695 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-10 00:15:38 +00:00
Dan Gohman
a70dca156f Factor out LiveIntervalAnalysis' code to determine whether an instruction 
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:27:56 +00:00
Benjamin Kramer
8bff4af612 Fix a use-after-free in post-ra-scheduling. 
MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-02 15:59:52 +00:00
David Goodwin
63bcbb72f7 All callee-saved registers are live-out of a return block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83223 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 23:28:47 +00:00
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 21:46:35 +00:00
David Goodwin
c7951f8e09 Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83208 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 19:45:32 +00:00
Evan Cheng
714e8bc1fc Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change 
operands of instructions with these properties while breaking anti-dep.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83198 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:26:23 +00:00
Reid Kleckner
c277ab08a2 Fix integer overflow in instruction scheduling. This can happen if we have 
basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:15:38 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:10:16 +00:00
Jakob Stoklund Olesen
544df3651e Use KILL instead of IMPLICIT_DEF in LowerSubregs pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 20:32:46 +00:00
David Goodwin
8f909345bc Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82629 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-23 16:35:25 +00:00
Evan Cheng
fb2e752e41 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. 
Not functionality change yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 21:02:19 +00:00