Commit Graph

118 Commits

Author SHA1 Message Date
89fd43778e Typo: Reviewed by Alistair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 18:14:32 +00:00
15ab3594eb Post-RA scheduler compile time fix. Quadratic computation of DAG node depth.
The post-ra scheduler was explicitly updating the depth of a node's
successors after scheduling it, regardless of whether the successor
was ready. This is quadratic for DAGs with transitively redundant
edges. I simply removed the useless update of depth, which is lazilly
computed later.
Fixes <rdar://problem/9044332> compiler takes way too long to build TextInput.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 17:09:08 +00:00
2da8bc8a5f Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
3ef1c8759a Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
90c579de5a Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 18:33:48 +00:00
1f74590e9d Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 00:23:35 +00:00
9ccaf53ada Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:42:04 +00:00
24173da61d Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 20:01:02 +00:00
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
774bc882fd - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 21:06:53 +00:00
729aab3dd3 Allow target to provide its own hazard recognizer to post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 00:12:18 +00:00
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:53:24 +00:00
76526f8863 Remove dbg_value workaround and associated command line option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:34:01 +00:00
de70b1f9be Enable preserving debug information through post-RA scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:47 +00:00
9001303a3f 80 column and trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:19:48 +00:00
5468e0928b add cmd line option to leave dbgvalues in during post-RA sceduling. Useful
while debugging what's mishandled about them in the post-RA pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:18:04 +00:00
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
8295d4c96c As a temporary workaround for post-RA not handling DebugValue instructions,
just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 00:49:11 +00:00
8b3d6682a4 Remove a #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12 16:26:03 +00:00
b0812f114b Fix some more places where dbg_value affected codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05 00:02:59 +00:00
e1b2129471 Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 01:26:01 +00:00
990d285765 <rdar://problem/7453528>. Track only physical registers that are valid for the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90970 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 17:18:22 +00:00
15d75d9f11 Don't hang on to pointers or references after vector::push_back.
The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03 01:49:56 +00:00
557bbe6b5d Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89471 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:32:48 +00:00
87d21b92fc Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 19:52:48 +00:00
12dd99dc30 Rename registers to break output dependencies in addition to anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87015 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 19:08:21 +00:00
c2e8a7e8d2 Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:48:55 +00:00
0855dee564 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:15:47 +00:00
54097836f3 Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86098 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-05 01:19:35 +00:00
4de099d8ca Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85939 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 20:57:50 +00:00
0ba90f3e34 Make -print-machineinstrs more readable.
- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 20:19:03 +00:00
82c7248518 Make AntiDepReg.h internal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85412 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28 18:29:54 +00:00
e10deca33e Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85166 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 22:31:16 +00:00
ada0ef86d9 Define virtual destructor in *.cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85146 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 19:41:00 +00:00
348777110a Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 19:32:42 +00:00
2e7be612d5 Break anti-dependence breaking out into its own class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26 16:59:04 +00:00
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 06:57:41 +00:00
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 06:33:48 +00:00
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
c1ae8c9b8f Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 01:44:44 +00:00
7441d14873 Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84691 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 22:50:43 +00:00
480c529e02 Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84658 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 19:54:44 +00:00
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 21:06:15 +00:00
c83da2f9e3 If post-alloc scheduler is not enabled, it should return false, not true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84248 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:10:34 +00:00
d452ea6a64 Add debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84011 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13 19:16:03 +00:00
5bf7c2a346 Fix a missing initialization of PostRAScheduler's AA member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83695 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-10 00:15:38 +00:00
a70dca156f Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:27:56 +00:00
8bff4af612 Fix a use-after-free in post-ra-scheduling.
MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 15:59:52 +00:00
63bcbb72f7 All callee-saved registers are live-out of a return block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 23:28:47 +00:00
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00