5 Commits

Author	SHA1	Message	Date
Jim Grosbach	e2999b4899	Revert 141203. InstCombine is looping on unit tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141209 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 20:44:29 +00:00
Jim Grosbach	30c1ff234d	Update InstCombine worklist after instruction transform is complete. ... When updating the worklist for InstCombine, the Add/AddUsersToWorklist functions may access the instruction(s) being added, for debug output for example. If the instructions aren't yet added to the basic block, this can result in a crash. Finish the instruction transformation before adjusting the worklist instead. rdar://10238555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141203 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 20:05:00 +00:00
Duncan Sands	ee9a2e322a	Have SimplifyBinOp dispatch Xor, Add and Sub to the corresponding methods ... (they had just been forgotten before). Adding Xor causes "main" in the existing testcase 2010-11-01-lshr-mask.ll to be hugely more simplified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122245 91177308-0d34-0410-b5e6-96231b3b80d8	2010-12-20 14:47:04 +00:00
Dan Gohman	d8e0c0438a	Really check that the bits that will become zero are actually already zero ... before eliminating the operation that zeros them. This fixes rdar://8739316. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121353 91177308-0d34-0410-b5e6-96231b3b80d8	2010-12-09 02:52:17 +00:00
Owen Anderson	648b20d5db	When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low ... bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117953 91177308-0d34-0410-b5e6-96231b3b80d8	2010-11-01 21:08:20 +00:00