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105 Commits

Author SHA1 Message Date
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 17:49:57 +00:00
Matt Arsenault
d0c1b54942 Fix return before else 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208510 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-11 21:24:41 +00:00
Tom Stellard
561bb44525 R600: Expand i64 SELECT_CC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208430 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-09 16:42:19 +00:00
Tom Stellard
87b983680c R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-09 16:42:16 +00:00
Matt Arsenault
459ff08eaa R600: Promote f64 vector load/stores to i64 for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208344 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-08 18:01:56 +00:00
Tom Stellard
4b84b524e5 R600: Expand i64 ISD:SUB 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208005 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-05 21:47:15 +00:00
Tom Stellard
ab2fed6622 R600: Expand vector sin and cos. 
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-02 15:41:47 +00:00
Tom Stellard
1d6859256c R600: Expand TruncStore i64 -> {i16,i8} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207844 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-02 15:41:46 +00:00
Tom Stellard
19a970b2da R600: optimize the UDIVREM 64 algorithm 
This is a squash of several optimization commits:
 - calculate DIV_Lo and DIV_Hi separately
 - use BFE_U32 if we are operating on 32bit values
 - use precomputed constants instead of shifting in UDVIREM
 - skip the first 32 iterations of udivrem

v2: Check whether BFE is supported before using it

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-29 23:12:46 +00:00
Tom Stellard
ea89cd8b52 R600: Implement iterative algorithm for udivrem 
Initial implementation, rather slow

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207588 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-29 23:12:45 +00:00
Tom Stellard
dbe7f8723a R600: Change UDIV/UREM to UDIVREM when legalizing types 
When legalizing ops, with UDIV/UREM set to expand, they automatically
expand to UDIVREM (if legal or custom).
We need to do this manually for legalize types.

v2:
  SI should be set to Expand because the type is legal, and it is
    automatically lowered to UDIVREM if UDIVREM is Legal/Custom
  R600 should set to UDIV/UREM to Custom because it needs to lower them
    during type legalization

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207587 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-29 23:12:43 +00:00
Tom Stellard
78fc9c53e5 R600: remove unused variable 
Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207586 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-29 23:12:38 +00:00
Craig Topper
7d811a53de Convert more SelectionDAG functions to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207397 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-28 05:57:50 +00:00
Craig Topper
a7f892b33b Convert SelectionDAG::getMergeValues to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207374 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-27 19:20:57 +00:00
Craig Topper
80d8db7a1f Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207327 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-26 18:35:24 +00:00
Matt Arsenault
d1f361aa39 R600: Fix function name printing in LowerCall 
v2: Check both ExternalSymbol and GlobalAddress

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207282 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-25 22:22:01 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-25 05:30:21 +00:00
Matt Arsenault
3682fdabef R600: Emit error instead of unreachable on function call 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206904 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 16:42:00 +00:00
Matt Arsenault
073440f3d4 R600: Change how vector truncating stores are packed. 
Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206864 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 04:11:14 +00:00
Matt Arsenault
3ddf868b04 R600: Make sign_extend_inreg legal. 
Don't know why I didn't just do this in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 03:49:30 +00:00
Tom Stellard
52d940edcd R600: Add comment clariying use of sext for result of MUL_U24 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206501 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-17 21:00:13 +00:00
Matt Arsenault
ff8d7fb136 R600: Expand sign extension of vectors. 
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.

v2: move setOperation() calls to R600ISelLowering.cpp.
    cleanup the SI code to make it obvious that this patch does is nop for SI

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206348 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-16 01:41:30 +00:00
Matt Arsenault
f8ea0352e0 R600/SI: Fix loads of i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206330 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 22:28:39 +00:00
Nick Lewycky
d63390cba1 Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206255 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 07:22:52 +00:00
Matt Arsenault
d879166376 Move ExtractVectorElements to SelectionDAG. 
This seems generally useful, and makes sense to
go along with SplitVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206041 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-11 17:47:30 +00:00
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 19:45:41 +00:00
Matt Arsenault
e3e086ea00 Use .data() instead of &x[0] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205722 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 16:44:24 +00:00
Matt Arsenault
193c3e91b9 R600: Compute masked bits for min and max 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205242 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 19:35:33 +00:00
Matt Arsenault
828bfc7350 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205236 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 18:21:18 +00:00
Matt Arsenault
894fa802f5 R600: Add target nodes for BFM and BFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 18:21:13 +00:00
Matt Arsenault
0c6d96cf16 R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:31 +00:00
Matt Arsenault
94687c0f43 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204945 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:24 +00:00
Matt Arsenault
e0e503801f R600: Add a testcase for sext_in_reg I missed. 
This sext_inreg i32 in i64 case was already handled, but not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-26 18:31:06 +00:00
Matt Arsenault
ab5382f5eb R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204743 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-25 18:18:27 +00:00
Matt Arsenault
6c199d8212 R600: Implement isNarrowingProfitable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 19:43:31 +00:00
Matt Arsenault
2683baa8ac R600: Match sign_extend_inreg to BFE instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 18:58:11 +00:00
Matt Arsenault
2345166d2f R600: Remove unnecessary attempt to zext a pointer. 
Private pointers are now always 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-15 00:08:26 +00:00
Matt Arsenault
2cf43de915 R600: Code cleanup. 
Use sign_extend_inreg and getZeroExtendInReg instead of
using the bit operations they expand into.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-15 00:08:22 +00:00
Matt Arsenault
054f4eccd2 R600: Fix trunc store from i64 to i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-12 18:45:52 +00:00
Matt Arsenault
0e5b4860b5 R600: Calculate store mask instead of using switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203527 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-11 01:38:53 +00:00
Matt Arsenault
cc1240ee1b Use .data() instead of &x[0] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203516 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-11 00:01:31 +00:00
Matt Arsenault
161e3a80b2 R600: Fix extloads from i8 / i16 to i64. 
This appears to only be working for global loads. Private
and local break for other reasons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:12 +00:00
Matt Arsenault
b4cd160bb9 R600/SI: Expand selects on vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:03 +00:00
Matt Arsenault
af0cc459bf Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203013 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-05 21:47:22 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 21:01:28 +00:00
Matt Arsenault
e87a1a9e2c Fix DOT4 missing from getTargetOpcodeName 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 21:01:21 +00:00
Tom Stellard
0f2e653317 R600/SI: Expand all v8[if]32 operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:15 +00:00
Benjamin Kramer
eee40f92a9 R600: Always implement both versions of isTruncateFree and add a sanity check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201222 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-12 10:17:54 +00:00
Matt Arsenault
700bba297b R600: Implement isTruncateFree 
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201107 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 19:57:42 +00:00
Tom Stellard
7d9ed1cac5 R600/SI: Expand i1 BR_CC 
This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.

I was unable to come up with a reduced test case for this.

https://bugs.freedesktop.org/show_bug.cgi?id=72785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200776 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-04 17:18:43 +00:00