4 Commits

Author	SHA1	Message	Date
Quentin Colombet	5b00f4edcb	Modify how the formulae are rated in Loop Strength Reduce. ... Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8	2013-05-31 17:20:29 +00:00
Dan Gohman	a34c885d51	Move x86-specific tests out of test/Transforms/LoopStrengthReduce and ... into test/CodeGen/X86, so that they aren't run when the x86 target is not enabled. Fix uglygep.ll to not be x86-specific. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110343 91177308-0d34-0410-b5e6-96231b3b80d8	2010-08-05 17:04:15 +00:00
Dan Gohman	e5f76877ae	When determining a canonical insert position, don't climb deeper ... into adjacent loops. Also, ensure that the insert position is dominated by the loop latch of any loop in the post-inc set which has a latch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100906 91177308-0d34-0410-b5e6-96231b3b80d8	2010-04-09 22:07:05 +00:00
Dan Gohman	f8d0578e4c	When emitting code for an add, don't force a SCEVUnknown wrapper around ... a hoisted intermediate result if the intermediate result isn't an Instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100884 91177308-0d34-0410-b5e6-96231b3b80d8	2010-04-09 19:14:31 +00:00