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Author SHA1 Message Date
Douglas Gregor
6ced1d12dd Add initial *-*-rtems* target, from Joel Sherrill 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 22:41:06 +00:00
Evan Cheng
385e930d55 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 22:36:09 +00:00
Evan Cheng
ce795dc92f Add MCSubtargetInfo target registry stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 22:25:04 +00:00
Dan Gohman
71997f303e Teach IVUsers to stop at non-affine expressions unless they are both 
outside the loop and reducible.

This more completely hides them from LSR, which isn't usually able to
do anything meaningful with non-affine expressions anyway, and this
consequently hides them from SCEVExpander, which is acutely unprepared
for non-affine expressions.

Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests
the new behavior.

This works around the bug in PR10117 / rdar://problem/9633149, and is
generally an improvement besides.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 22:05:19 +00:00
Owen Anderson
f1ac465b67 Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of integers, and fix the one optimization pass that I'm aware of that needs updating for this. At least one current target, ARM NEON, can implement these operations on vectors directly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134265 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 21:52:38 +00:00
Eli Friedman
adebeeaaee Calling-convention specifications for illegal types are no-ops. Simplify based on this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 21:33:28 +00:00
Jim Grosbach
a7603982db ARMv7M vs. ARMv7E-M support. 
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 21:12:19 +00:00
Evan Cheng
5b1b4489cf Rename TargetSubtarget to TargetSubtargetInfo for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 21:01:15 +00:00
Evan Cheng
94214703d9 - Added MCSubtargetInfo to capture subtarget features and scheduling 
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 20:45:01 +00:00
Jim Grosbach
eb03c3b228 Fix off-by-one error. 
(low two bits always zero, so off by one bit of encoded value).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 19:07:09 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 17:57:27 +00:00
Jim Grosbach
efeedceb41 Pseudo-ize t2MOVCC[ri]. 
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 17:14:11 +00:00
Evan Cheng
4d9af61a48 Eliminate one extra conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 16:59:30 +00:00
Duncan Sands
ed5bc470aa Disable commit 134216 ("Add 134199 back, but disable the optimization when the second 
copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 12:01:00 +00:00
Francois Pichet
24e11afad2 Another misuse of StringRef. MSVC is very sensitive to that kind of error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 09:23:41 +00:00
Nick Lewycky
394d1f1948 Fix likely typo, reduce number of instruction name collisions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 06:27:03 +00:00
Rafael Espindola
3f9b9eb57d Fix use after free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 04:40:50 +00:00
Rafael Espindola
8f1bdac3eb Avoid DenseMap lookup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134231 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 04:15:02 +00:00
Rafael Espindola
fe11caaa73 Fix off by one error. I misunderstood the comment about killedAt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134229 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 03:31:29 +00:00
Rafael Espindola
1c8b97cbc0 Check the liveinterval, not the kill flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 02:35:06 +00:00
Jakob Stoklund Olesen
5e9ae090d8 Don't inflate register classes used by inline asm. 
The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.

For now, just give up on regclass inflation when inline asm is involved.

No test case, this bug hasn't happened yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 01:24:25 +00:00
Akira Hatanaka
c4f24eb584 Improve Mips back-end's handling of DBG_VALUE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 01:04:43 +00:00
Dan Gohman
68c0dbc14f Improve constant folding of undef for cmp and select operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 01:03:43 +00:00
Eric Christopher
5e653c925c Add support for the 'j' immediate constraint. This is conditionalized on 
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 01:00:07 +00:00
Dan Gohman
30cb6dda5a Improve constant folding of undef for binary operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:42:17 +00:00
Eric Christopher
d5dc9eca2b Add support for the ARM 't' register constraint. And another testcase 
for the 'x' register constraint.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:30:46 +00:00
Evan Cheng
e1bff38386 Switch SubtargetFeatures from std::string to StringRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134219 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:23:10 +00:00
Eric Christopher
1070f82569 We'll return a null RC by default if we can't match. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:19:27 +00:00
Rafael Espindola
0c13e9471a Add 134199 back, but disable the optimization when the second copy is a kill. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:16:54 +00:00
Eric Christopher
89bd71fc53 Add support for the 'x' constraint. 
Part of rdar://9307836 and rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-01 00:14:47 +00:00
Bill Wendling
c3882164cb Remove tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:59:38 +00:00
Eric Christopher
09b4467ac5 Capitalize the unsigned part of the initializer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:59:16 +00:00
Eric Christopher
35e6d4d6b6 Rename Pair to RCPair lacking any better naming ideas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:50:52 +00:00
Bill Wendling
e08d4335ad Improve comment: Show the register the DWARF label is added to. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:47:40 +00:00
Bill Wendling
2374cb8e7d Use the correct registers on X86_64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:47:14 +00:00
Jakob Stoklund Olesen
098c7ac7c8 Fix a problem with fast-isel return values introduced in r134018. 
We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:42:18 +00:00
Jim Grosbach
2a7b41ba4d Refact ARM Thumb1 tMOVr instruction family. 
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:38:17 +00:00
Eric Christopher
73744df0c4 Add support for the 'h' constraint. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:23:01 +00:00
Bill Wendling
5cd2791513 Add target a target hook to get the register number used by the compact unwind 
encoding for the registers it knows about. Return -1 if it can't handle that
register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:20:32 +00:00
Rafael Espindola
15e96be3c7 Revert my previous patch while I debug llvm-gcc bootstrap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:58:17 +00:00
Bill Wendling
d221cd676b Add one more comment to the FDE verbose asm output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:35:49 +00:00
Rafael Espindola
c747acb8d9 Don't give up on coalescing A and B when we find 
A = X
B = X

Instead, proceed as if we had found

A = X
B = A

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:24:13 +00:00
Eric Christopher
a8cca80d4a Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>. 
No functional change.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:17:01 +00:00
Jim Grosbach
63b46faeb8 Thumb1 register to register MOV instruction is predicable. 
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:10:46 +00:00
Bill Wendling
2541c41f3e Add comments to the FDE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:02:20 +00:00
Bill Wendling
efd24ddbff Add more comments to the ASM output for the CIE's "moves". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 21:45:12 +00:00
Jakob Stoklund Olesen
1bd622132b Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 21:30:30 +00:00
Bill Wendling
3c163cfa60 Add comments to the ASM output to help understand the compact unwind and CIE tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 21:25:51 +00:00
Rafael Espindola
cfe5254cd3 Create a isFullCopy predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 21:15:52 +00:00
Rafael Espindola
77a2c372fa Add r134057 back, but splice the predecessor after the successors phi 
nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 20:14:24 +00:00