Commit Graph

3174 Commits

Author SHA1 Message Date
Zoran Jovanovic
5d945dbe5e Fixed encoding of SYSCALL microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:17:08 +00:00
Zoran Jovanovic
8f883ae9d3 Revert revision 202518 because of wrong commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:14:16 +00:00
Zoran Jovanovic
60f8980545 Fix operand of SC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:02:17 +00:00
Sasa Stankovic
068a8c145a [mips] Implement NaCl sandboxing of indirect jumps:
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer).
  * Add masking instructions before indirect jumps (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2847


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 10:00:38 +00:00
Alp Toker
bf930d5c1f Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 04:21:15 +00:00
Saleem Abdulrasool
6631253907 Asm Parser: support .error directive
The .error directive is similar to .err in that it will halt assembly if it is
evaluated for assembly.  However, it permits a user supplied message to be
rendered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201999 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 23:02:23 +00:00
Saleem Abdulrasool
e3d661f547 AsmParser: support .ifeqs directive
The .ifeqs directive assembles the following code if the quoted string
parameters are equal.  The strings must be quoted using double quotes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201998 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 23:02:18 +00:00
Saleem Abdulrasool
ec1c80576d ARM IAS: support .align without parameters
.align is handled specially on certain targets.  .align without any parameters
on ARM indicates a default alignment (4).  Handle the special case in the target
parser, but fall back to the generic parser for the normal version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:32 +00:00
Saleem Abdulrasool
69f706d9e1 MCAsmParser: support .ifne
The .ifne directive assembles the following section of code if the argument
expression is non-zero.  Effectively, it is equivalent to if.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 15:53:41 +00:00
Saleem Abdulrasool
0922e5b643 MCAsmParser: handle space properly for .ifc/.ifnc
If the strings are not quoted, the first string stops at the first comma, and
the second string stops at the end of the line.  Strings which contain
whitespace should be quoted.  Unquoted space is to be discarded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201985 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 15:53:36 +00:00
Saleem Abdulrasool
a0d16299c9 MCAsmParser: add support for .err directive
The .err directive produces an error whenever it is assembled.  This can be
useful for preventing assembly when an unexpected condition occurs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201984 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 15:53:30 +00:00
Saleem Abdulrasool
be66089390 ARM IAS: support .short and .hword
This adds support for the .short and its alias .hword for adding literal values
into the object file.  This is similar to the .word directive, however, rather
than inserting a value of 4 bytes, adds a 2-byte value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201968 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 06:22:09 +00:00
Nico Rieck
fa3089b14c MC: Support COFF string tables larger than 10MB
Offsets past the range of single-slash encoding are encoded as base64,
padded to 6 characters, and prefixed with two slashes. This encoding is
undocumented but used by MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201940 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-22 16:12:20 +00:00
Daniel Sanders
5c86661f15 [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.
Summary:
This removes the need to coerce UnknownABI to the default ABI (O32 for
MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser.

Clang has been updated to disable both possible default ABI's before enabling
the ABI it intends to use.

[*] N64 being the default for MIPS64 is not actually correct.
    However N32 is not fully implemented/tested yet.

Depends on: D2830

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2832
Differential Revision: http://llvm-reviews.chandlerc.com/D2846



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 14:58:19 +00:00
Benjamin Kramer
59f6c76703 AsmParser: Disable Darwin-style macro argument expansion on non-darwin targets.
There is code in the wild that relies on $0 not being expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 13:36:32 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 06:34:39 +00:00
Daniel Sanders
210edf5559 [mips] Add explicit N32 and N64 tests to nabi-regs.s test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 15:30:54 +00:00
Craig Topper
fa0cf99585 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 08:25:02 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Saleem Abdulrasool
156f2a1f5d MCAsmParser: support required parameters
This enhances the macro parser to parse and handle parameter qualifications,
which is needed to support required formal parameters in macro definitions.  A
required parameter may not be defaulted (though providing a default value is
accepted with a warning).  This improves GAS compatibility.

Partially addresses PR9248.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201630 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 03:00:29 +00:00
Kevin Enderby
4959a2d878 Fix the arm assembler so that this malformed instruction:
ldrd r6, r7 [r2, #15]
simply gives an error and does not triggers an assertion.

As Jim points out, the diagnostic is really strange here,
but fixing that would be more complicated. The missing
comma results in the parser expecting a construct like r2[2],
which is the vector index thing the error message is talking
about. That's not what the user intended, though, and there's
nothing else in the instruction that looks at all like a vector.
Yet more fallout from not having a real parser here and trying
to do context-free generic matching for addressing modes.

rdar://15097243


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 21:45:27 +00:00
Anders Waldenborg
1410f7ffc6 Add support for assigning to . in AsmParser.
This is implemented by handling assignments to the '.' pseudo symbol
as ".org" directives.

Differential Revision: http://llvm-reviews.chandlerc.com/D2625



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 20:48:32 +00:00
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 10:03:43 +00:00
Saleem Abdulrasool
62cb90e8c6 MCAsmParser: add some mixed argument tests
Add some tests to explicitly validate handling of comma and non-comma separated
arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 00:40:22 +00:00
Saleem Abdulrasool
696002f3b4 MCAsmParser: better handling for named arguments
Until this point only macro definition with named parameters were parsed but the
names were ignored.  This adds support for using that information for named
parameter instantiation.

In order to support the full semantics of the keyword arguments, the arguments
are no longer lazily initialised since the keyword arguments can be specified
out of order and partially if they are defaulted.  Prepopulate the arguments
with the default value for any defaulted parameters, and then parse the
specified arguments.

This simplies some of the handling of the arguments in the inner loop since
empty arguments simply increment the parameter index and move on.

Note that keyword and positional arguments cannot be mixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 00:40:17 +00:00
Nico Rieck
268e96a8a6 Fix broken CHECK lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 07:31:05 +00:00
Saleem Abdulrasool
5a39da0a6f MCAsmParser: relax declaration parsing
The Linux kernel defines empty macros for compatibility with ARM UAL syntax.
The comma after the name is optional, and if present can be safely lexed.  This
improves compatibility with the GNU assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 04:56:31 +00:00
Saleem Abdulrasool
1edea19210 ARM IAS: (partially) support .arch_extension directive
This adds a partial implementation of the .arch_extension directive to the
integrated ARM assembler.  There are a number of limitations to this
implementation arising from the target backend support rather than the
implementation itself.  Namely, iWMMXT (v1 and v2), Maverick, and XScale support
is not present in the ARM backend.  Currently, there is no check for A-class
only (needed for virt), and no ARMv6k detection (needed for os and sec).  The
remainder of the extensions are fully supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 00:16:41 +00:00
Craig Topper
0877c6575a Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-15 07:29:18 +00:00
Diego Novillo
837c54fa7b Support DWARF discriminators in object streamer.
Summary:
This adds support for emitting DWARF path discriminator values in
the object streamer. It also changes the DWARF dumper to show
discriminator values in the line table output.

Reviewers: echristo

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 19:27:53 +00:00
Diego Novillo
3e5fe1426a Simplify checks in MC/AsmParser/directive_loc.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201361 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 20:16:42 +00:00
Diego Novillo
86dd0f939f Fix generation of 'isa' and 'discriminator' keywords.
Summary:
There should be a space before each of these two keywords to avoid
generating invalid assembly files.

NOTE: I could not find an obvious maintainers in CODE_OWNERS.TXT, but
      this seems related to debug info.

Reviewers: echristo

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2791

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 20:05:03 +00:00
Jim Grosbach
75bf592807 Tidy up a bit. Formatting only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 20:48:41 +00:00
Jim Grosbach
0c2ff8cbfd ARM: Thumb2 LDR(literal) can target SP.
Fix a slightly overzealous destination register restriction for the
'without .w' alias. Add some explicit testcases.

rdar://16033140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 20:48:39 +00:00
Elena Demikhovsky
e4092e9895 AVX-512: Optimized BUILD_VECTOR pattern;
fixed encoding of VEXTRACTPS instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 07:25:59 +00:00
Chad Rosier
5fcb5c92d3 [AArch64] Handle aliases of conditional branches without b.pred form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 15:43:11 +00:00
Matheus Almeida
3f14ca5e30 [mips][msa] Add DLSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 12:05:17 +00:00
Craig Topper
ced2756280 Recommit r201059 and r201060 with hopefully a fix for its original failure.
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 06:55:41 +00:00
Benjamin Kramer
275f653307 AsmParser: Parse (and ignore) nested .macro definitions.
This enables a slightly odd feature of gas. The macro is defined when
the outermost macro is instantiated.

PR18599

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201045 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-09 16:22:00 +00:00
Saleem Abdulrasool
91ec991b45 ARM: change attribute tests to use parsed form
This makes the tests more readable by using the -arm-attributes decoding support
in llvm-readobj since that is now available.  Change the invocation commands to
be similar to other test and use a more precise triple (the tests only require
ARM EABI support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-08 23:17:02 +00:00
Renato Golin
703197fc94 Remove -arm-disable-ehabi option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 20:12:49 +00:00
Sasa Stankovic
fba9c104b9 Changed comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 11:16:02 +00:00
Venkatraman Govindaraju
1826a52645 [Sparc] Add support for parsing synthetic instruction 'mov'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200965 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 09:06:52 +00:00
Venkatraman Govindaraju
464d664971 [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200963 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 07:34:49 +00:00
Kevin Enderby
a2f4bb9077 Update the X86 assembler for .intel_syntax to accept
the << and >> bitwise operators.

rdar://15975725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200896 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 01:21:15 +00:00
Logan Chien
575c4addce ARM: Resolve thumb_bl fixup in same MCFragment.
In Thumb1 mode, bl instruction might be selected for branches between
basic blocks in the function if the offset is greater than 2KB.
However, this might cause SEGV because the destination symbol
is not marked as thumb function and the execution mode will be reset
to ARM mode.

Since we are sure that these symbols are in the same data fragment, we
can simply resolve these local symbols, and don't emit any relocation
information for this bl instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 14:15:16 +00:00
Elena Demikhovsky
1ee5ca7005 AVX-512: fixed a bug in EVEX encoding (the bug appeared after r200624)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 13:03:01 +00:00
Petar Jovanovic
7f15e90281 [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200783 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 18:41:57 +00:00
David Woodhouse
2d53a37573 MC: Fix .octa output for APInts with BitWidth > 128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-01 16:52:33 +00:00
David Woodhouse
075a90a913 MC: Add support for .octa
This is a minimal implementation which accepts only constants rather than
full expressions, but that should be perfectly sufficient for all known
users for now.

Patch from PaX Team <pageexec@freemail.hu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-01 16:20:59 +00:00
David Majnemer
f34dc1b514 Update a .fill test to use the updated semantics.
Something funny happened, this should've been part of r200606.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-01 07:36:52 +00:00
David Majnemer
e18fc7bc2d MC: Improve the .fill directive's compatibility with GAS
Per the GAS documentation, .fill should permit pattern widths that
aren't a power of two. While I was in the neighborhood, I added some
sanity checking. This change was motivated by a use of this construct
in the Linux Kernel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-01 07:19:38 +00:00
Rafael Espindola
ac9f143a69 Remove another hasRawTextSupport.
To remove this one simply move the end of file logic from the asm printer to
the target mc streamer.

This removes the last call to hasRawTextSupport from lib/Target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 23:10:26 +00:00
Matheus Almeida
9c45241485 [mips][msa] Add insert.d instruction.
This instruction is only available on Mips64 cores that implement the MSA ASE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 13:31:20 +00:00
Craig Topper
2bb06b0002 Move address override handling in X86MCCodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 05:33:45 +00:00
David Woodhouse
93f81d9b33 [x86] Fix signed relocations for i64i32imm operands
These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32.
Kill the horrid and incomplete special case and FIXME in
EncodeInstruction() and set things up so it can infer the signedness
from the ImmType just like it can the size and whether it's PC-relative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 22:20:41 +00:00
Timur Iskhodzhanov
4e54e6fe75 Fix PR18381 - print a minimal diagnostic rather than assert on unresolved .secidx target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200490 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 21:13:05 +00:00
Saleem Abdulrasool
09f38a0ef1 ARM IAS: support .object_arch
The .object_arch directive indicates an alternative architecture to be specified
in the object file.  The directive does *not* effect the enabled feature bits
for the object file generation.  This is particularly useful when the code
performs runtime detection and would like to indicate a lower architecture as
the requirements than the actual instructions used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:46:41 +00:00
Saleem Abdulrasool
7a38b33dec ARM IAS: support .movsp
.movsp is an ARM unwinding directive that indicates to the unwinder that a
register contains an offset from the current stack pointer.  If the offset is
unspecified, it defaults to zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:46:24 +00:00
Saleem Abdulrasool
2c9ed5d050 ARM: suuport .tlsdescseq directive
This enhances the ARMAsmParser to handle .tlsdescseq directives.  This is a
slightly special relocation.  We must be able to generate them, but not consume
them in assembly.  The relocation is meant to assist the linker in generating a
TLS descriptor sequence.  The ELF target streamer is enhanced to append
additional fixups into the current segment and that is used to emit the new
R_ARM_TLS_DESCSEQ relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200448 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:47 +00:00
Saleem Abdulrasool
4747d6b0a5 ARM: support TLS descriptor relocations
Add support for tlsdesc relocations which are part of the ABI, marked as
experimental.  These relocations permit the linker to perform TLS reference
optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:38 +00:00
Saleem Abdulrasool
9629ad3005 ARM: support tlscall relocations
This adds support for TLS CALL relocations.  TLS CALL relocations are used to
indicate to the linker to generate appropriate entries to resolve TLS references
via an appropriate function invocation (e.g. __tls_get_addr(PLT)).

In order to accomodate the linker relaxation of the TLS access model for the
references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete.
This requires that the partial inplace value is also incomplete (i.e. 0).  We
simply avoid the offset value calculation at the time of the fixup adjustment in
the ARM assembler backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200446 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:31 +00:00
David Majnemer
654247c3ea MC: Better management of macro arguments
The linux kernel makes uses of a GAS `feature' which substitutes nothing
for macro arguments which aren't specified.

Proper support for these kind of macro arguments necessitated a cleanup of
differences between `GAS' and `Darwin' dialect macro processing.

Differential Revision: http://llvm-reviews.chandlerc.com/D2634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200409 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 18:57:46 +00:00
Matheus Almeida
72d4223ff5 [mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 15:12:02 +00:00
Matheus Almeida
ba67c2a4ee [mips][msa] Add copy_{u,s}.d.
These instructions are only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 14:05:28 +00:00
Renato Golin
3fca788967 Enable EHABI by default
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 11:50:56 +00:00
David Majnemer
b04ddad8ea MC: Reorganize macro MC test along dialect lines
This commit seeks to do two things:
 - Run the surfeit of tests under the Darwin dialect.  This ends up
   affecting tests which assumed that spaces could deliminate arguments.
 - The GAS dialect tests should limit their surface area to things that
   could plausibly work under GAS. For example, Darwin style arguments
   have no business being in such a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200383 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 09:18:43 +00:00
David Woodhouse
634295bcb6 Tests for mode switching
1. test that inlineasm works
2. test that relaxable instructions are re-encoded in the correct mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:13:30 +00:00
Matheus Almeida
4ed4bd0fee [mips] Fix ELF header flags.
As opposed to GCC/GAS the default ABI for Mips64 is n64.
Compatibility bit should be set if o32 ABI is used when targeting Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200332 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 19:24:11 +00:00
Mark Seaborn
66aefa805b ARM MC: Fix the initial DWARF CFI unwind info at the start of a function
This brings MC into line with GNU 'as' on ARM, and it brings the ARM
target into line with most other LLVM targets, which declare the
initial CFI state with addInitialFrameState().

Without this, functions generated with .cfi_startproc/endproc on ARM
will tend to cause GDB to abort with:
  gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule.

I've also tested this by comparing the output of "readelf -w" on the
object files produced by llvm-mc and gas when given the .s file added
here.

This change is part of addressing PR18636.

Differential Revision: http://llvm-reviews.chandlerc.com/D2597

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 22:38:14 +00:00
David Majnemer
0fd23cd6c2 MC: Add support for .cfi_startproc simple
This commit allows LLVM MC to process .cfi_startproc directives when
they are followed by an additional `simple' identifier. This signals to
elide the emission of target specific CFI instructions that would
normally occur initially.

This fixes PR16587.

Differential Revision: http://llvm-reviews.chandlerc.com/D2624


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200227 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 17:20:25 +00:00
Saleem Abdulrasool
283b40e4d4 MC: fix test locations/name
Placed the MC variant diagnostics in the wrong directory accidentally.  Move
them into their respective architecture specific directories.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 22:55:02 +00:00
Saleem Abdulrasool
4fefc13b5e ARM: improve diagnostics for .word directive
If a complex expression was passed to the .word directive and the first part of
the directive failed to parse, a secondary diagnostic would be produced that
would clutter the error diagnostics.  Improve the diagnostics by consuming the
remainder of the statement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200160 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 22:29:50 +00:00
Saleem Abdulrasool
10096880c8 AsmParser: improve diagnostics for invalid variants
An emitted diagnostic for an invalid relocation variant would place the caret on
the token following the relocation variant indicator or at the end of the line
if there was no following token.  This change corrects the placement of the
caret to point to the token.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200159 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 22:29:43 +00:00
Rafael Espindola
5356e75b5b Implement the missing bits corresponding to .mips_hack_elf_flags.
These were:
* noreorder handling on the target object streamer and asm parser.
* setting the initial flag bits based on the enabled features.
* setting the elf header flag for micromips

It is *really* depressing I am the one doing this instead of someone at
mips actually taking the time to understand the infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200138 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:57:13 +00:00
Rafael Espindola
d41a30ed8c Move tests that just use llc from test/MC/Mips to test/MC/Codegen.
This is an expanded version of r200064.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 04:08:47 +00:00
Venkatraman Govindaraju
97f2a5e52a [Sparc] Add support for sparc relocation types in ELF object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200112 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 03:21:28 +00:00
Artyom Skrobov
85ae0340ba Reverting r199886 (Prevent repetitive warnings for unrecognized processors and features)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 16:56:18 +00:00
Rafael Espindola
86b535b085 This reverts commit r200064 and r200051.
r200064 depends on r200051.

r200051 is broken: I tries to replace .mips_hack_elf_flags, which is a good
thing, but what it replaces it with is even worse.

The new emitMipsELFFlags it adds corresponds to no assembly directive, is not
marked as a hack and is not even printed to the .s file.

The patch also introduces more uses of hasRawTextSupport.

The correct way to remove .mips_hack_elf_flags is to have the mips target
streamer handle the default flags (and command line options). That way the
same code path is used for asm and obj. The streamer interface should *really*
correspond to what is printed in the .s file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200078 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 15:06:56 +00:00
Jack Carter
8fe060da52 [Mips] Move 2 test cases from MC to CodeGen.
No code changes. Just reassignment of test case files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 02:14:14 +00:00
Jack Carter
998052555a [Mips] TargetStreamer ELF flag Support for default and commandline options.
This patch uses a common MipsTargetSteamer interface for both 
MipsAsmPrinter and MipsAsmParser for recording default and commandline
driven directives that affect ELF header flags.

It has been noted that the .ll tests affected by this patch belong in
test/Codegen/Mips. I will move them in a separate patch.

Also, a number of directives do not get expressed by AsmPrinter in the 
resultant .s assembly such as setting the correct ASI. I have noted this
in the tests and they will be addressed in later patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200051 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 00:24:07 +00:00
Alp Toker
ae43cab6ba Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 17:20:08 +00:00
Venkatraman Govindaraju
8c6a26194b [Sparc] Correct quad register list in the asm parser.
Add test cases to check parsing of v9 double registers and their aliased quad registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199974 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 05:24:01 +00:00
Kevin Enderby
7772f9af13 Update the X86 assembler for .intel_syntax to produce an error for invalid base
registers in memory addresses that do not match the index register. As it does
for .att_syntax.

rdar://15887380


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199948 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 22:34:42 +00:00
Kevin Enderby
2f49a7b24b Update the X86 assembler for .intel_syntax to produce an error for invalid
scale factors in memory addresses. As it does for .att_syntax.

It was producing:
Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133.

rdar://14967214


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199942 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 21:52:41 +00:00
Artyom Skrobov
93681fa6c6 Prevent repetitive warnings for unrecognized processors and features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 11:31:38 +00:00
Jack Carter
2ccf523ce7 [Mips] TargetStreamer Support for .set mips16.
This patch updates .set mips16 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that the assembler uses for
both ELF and ASCII output for these directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199851 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 23:08:42 +00:00
David Woodhouse
0ff018e500 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199809 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:55 +00:00
David Woodhouse
af588b9f0e [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199808 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:49 +00:00
David Woodhouse
51cd16cbd5 [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199807 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:42 +00:00
David Woodhouse
674140fc3e ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:36 +00:00
David Woodhouse
6abfcfe155 [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199805 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:27 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:08 +00:00
David Majnemer
ce5f07f33c Forgot to add testcase for r198590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199765 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 20:39:11 +00:00
Saleem Abdulrasool
d28c094c80 tools: support decoding ARM EHABI opcodes in readobj
Add support to llvm-readobj to decode the actual opcodes.  The ARM EHABI opcodes
are a variable length instruction set that describe the operations required for
properly unwinding stack frames.

The primary motivation for this change is to ease the creation of tests for the
ARM EHABI object emission as well as the unwinding directive handling in the ARM
IAS.

Thanks to Logan Chien for an extra test case!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199708 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 02:33:15 +00:00
Saleem Abdulrasool
e502a6aad3 ARM IAS: add support for .unwind_raw directive
This implements the unwind_raw directive for the ARM IAS.  The unwind_raw
directive takes the form of a stack offset value followed by one or more bytes
representing the opcodes to be emitted.  The opcode emitted will interpreted as
if it were assembled by the opcode assembler via the standard unwinding
directives.

Thanks to Logan Chien for an extra test!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199707 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 02:33:10 +00:00
Saleem Abdulrasool
27276437ae ARM IAS: support .personalityindex
The .personalityindex directive is equivalent to the .personality directive with
the ARM EABI personality with the specific index (0, 1, 2).  Both of these
directives indicate personality routines, so enhance the personality directive
handling to take into account personalityindex.

Bonus fix: flush the UnwindContext at the beginning of a new function.

Thanks to Logan Chien for additional tests!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 02:33:02 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al.
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:53 +00:00
David Woodhouse
a3fb0f9773 [x86] Fix 16-bit disassembly of JCXZ/JECXZ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:48 +00:00