Jim Laskey
f8913f19ae
Basic array support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26451 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 17:53:02 +00:00
Chris Lattner
0f6ab6ff97
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 07:14:48 +00:00
Chris Lattner
00d18f0879
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 06:36:20 +00:00
Chris Lattner
5126984b1d
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 05:50:56 +00:00
Chris Lattner
8c13d0a573
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:57:39 +00:00
Chris Lattner
2466472a2b
Add support for target-specific dag combines
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:53:38 +00:00
Chris Lattner
00ffed0468
Add interfaces for targets to provide target-specific dag combiner optimizations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:52:55 +00:00
Chris Lattner
5750df9d69
Add a new AddToWorkList method, start using it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26441 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:03:14 +00:00
Chris Lattner
0b1a85f110
Pull shifts by a constant through multiplies (a form of reassociation),
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implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26440 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 03:44:24 +00:00
Evan Cheng
d30bf01e90
Vector op lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:11:20 +00:00
Evan Cheng
860771d2d8
Vector ops lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:09:54 +00:00
Evan Cheng
f338dd881f
New type v2f32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26435 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:06:22 +00:00
Evan Cheng
1ab7d859cf
- Added VConstant as an abstract version of ConstantVec.
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- All abstrct vector nodes must have # of elements and element type as their
first two operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26432 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 00:51:13 +00:00
Evan Cheng
aafc1412b1
Another entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26430 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 23:38:49 +00:00
Evan Cheng
8c03fe4aca
Don't match x << 1 to LEAL. It's better to emit x + x.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 21:13:57 +00:00
Jim Laskey
45ccae5b7d
Add const, volatile, restrict support.
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Add array of debug descriptor support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26428 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 20:15:07 +00:00
Chris Lattner
06e1e25368
Fix a regression in a patch from a couple of days ago. This fixes
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Transforms/InstCombine/2006-02-28-Crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26427 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 19:47:20 +00:00
Chris Lattner
bf751e2d6f
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
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but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 07:08:22 +00:00
Chris Lattner
35a9f5a241
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:49:37 +00:00
Chris Lattner
f4c8575c27
remove implemented item
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:36:04 +00:00
Chris Lattner
15045b6973
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
Chris Lattner
71d9ebcbc1
fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26416 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:23:04 +00:00
Chris Lattner
9794392781
Implement rem.ll:test[7-9] and PR712
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26415 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 05:49:21 +00:00
Chris Lattner
6c9951b0da
Simplify some code now that the RHS of a rem can't be 0
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26413 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 05:40:55 +00:00
Chris Lattner
19ccd5c757
Rearrange some code, fold "rem X, 0", implementing rem.ll:test6
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26411 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 05:30:45 +00:00
Chris Lattner
22873462c9
Add support for output memory constraints.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 23:45:39 +00:00
Jim Laskey
9a777a3a8e
Qualify dwarf namespace inside llvm namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26409 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 22:37:23 +00:00
Nate Begeman
6e53ceb0d4
readme updates
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 22:08:36 +00:00
Jim Laskey
8a8e9756c8
Partial enabling of functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26404 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 20:37:42 +00:00
Chris Lattner
a34544d96c
Don't print constant initializers, they may span lines now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 20:09:23 +00:00
Jim Laskey
bd76184e67
Supporting multiple compile units.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26402 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 17:27:12 +00:00
Jim Laskey
0d086af82b
Re-orging file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26401 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 12:43:29 +00:00
Jim Laskey
38a409c7ae
Pretty print large struct constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26400 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 10:33:53 +00:00
Jim Laskey
dae29989cf
Removed dependency on how operands are printed (want multi-line.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 10:29:04 +00:00
Chris Lattner
3e88a4d700
Merge two almost-identical pieces of code.
...
Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand. This lets us fold this:
int %test23(int %a) {
%tmp.1 = and int %a, 1
%tmp.2 = seteq int %tmp.1, 0
%tmp.3 = cast bool %tmp.2 to int ;; xor tmp1, 1
ret int %tmp.3
}
into: xor (and a, 1), 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26396 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 02:38:23 +00:00
Chris Lattner
26ab9a9218
Fold (A^B) == A -> B == 0
...
and (A-B) == A -> B == 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26394 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 01:44:11 +00:00
Chris Lattner
a6bc5a4d21
Implement bit propagation through sub nodes, this (re)implements
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PowerPC/div-2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 01:00:42 +00:00
Chris Lattner
2d2536c9d7
remove some completed notes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26390 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 00:39:31 +00:00
Chris Lattner
81cd35586f
Check RHS simplification before LHS simplification to avoid infinitely looping
...
on PowerPC/small-arguments.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 00:36:27 +00:00
Chris Lattner
5f0c658aa4
Just like we use the RHS of an AND to simplify the LHS, use the LHS to
...
simplify the RHS. This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:
_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr
instead of this:
_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 00:22:28 +00:00
Chris Lattner
ec665151b8
Add a bunch of missed cases. Perhaps the most significant of which is that
...
assertzext produces zero bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 23:36:02 +00:00
Chris Lattner
02bd1b3e94
Fold (X|C1)^C2 -> X^(C1|C2) when possible. This implements
...
InstCombine/or.ll:test23.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26385 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 19:57:54 +00:00
Jim Laskey
c13a72c329
Reverting. Didn't realize some developers were embedding constants in their
...
target assembler code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26383 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 10:16:05 +00:00
Evan Cheng
140a4c4868
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 09:12:34 +00:00
Evan Cheng
38b7327ec0
Print ConstantPoolSDNode offset field.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26381 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 08:36:57 +00:00
Evan Cheng
a09bd8190c
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 08:28:12 +00:00
Jim Laskey
a3f332bdc3
Format large struct constants for readability.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26379 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 12:27:03 +00:00
Evan Cheng
51a9ed9b41
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:09:08 +00:00
Evan Cheng
53f280a30e
Updates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:04:07 +00:00
Evan Cheng
71fb834b50
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-25 10:02:21 +00:00