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42144 Commits

Author SHA1 Message Date
Owen Anderson
745c872bb5 Fix a warning when building with clang++. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115924 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 17:04:18 +00:00
Kalle Raiskila
218c98c284 Add the missing cases to the type->registerclass conversion function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115921 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 16:32:42 +00:00
Kalle Raiskila
8a52fa674b Implement two virtual functions in SPUTargetLowering. 
Before the implementation of isLegalAddressingMode, some rare cases 
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a 
bad TargetLowering, or if the bug is elsewhere and this patch just 
hides it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 16:24:35 +00:00
NAKAMURA Takumi
86c3647ddf Minor cosmetic change: fix DOSish \r\n. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115910 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 07:21:04 +00:00
Michael J. Spencer
b5814a3c15 MC-COFF: Fix symbol aliases. Fixes PR8251. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115909 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 06:29:33 +00:00
Eric Christopher
ee56ea6243 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 05:50:44 +00:00
Eric Christopher
5d18d92aad Use the correct register class here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 05:39:19 +00:00
Eric Christopher
338c253d7e Use the thumb2 conditional move instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 05:31:49 +00:00
Eric Christopher
1107734e22 Remove in-progress assertion, add TODO. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 05:14:08 +00:00
Owen Anderson
71802344fc Move the pass initialization helper functions into the llvm namespace, and add 
a header declaring them all.  This is also where we will declare per-library pass-set
initializer functions down the road.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 04:13:08 +00:00
Evan Cheng
5a50ceeaea Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:50:48 +00:00
Chris Lattner
b046810fe4 add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS, 
allowing us to convert ADD over.  deletes 160 lines of .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1 Fix a few issues in ArithBinOpEFLAGS that made it specific to and. 
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de Convert 'and' to single instance of a multipattern 
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:10:20 +00:00
Jim Grosbach
a4257162be Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:53:56 +00:00
Chris Lattner
511c686f76 add a new BinOpAI class to represent the immediate form that directly acts on EAX. 
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:43:39 +00:00
Jim Grosbach
3bbdcea49a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:42:42 +00:00
Chris Lattner
1bb9adae4c add a bunch of classes for other common patterns. 
As usual, no change in generated .inc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:35:28 +00:00
Owen Anderson
cce7f7cd03 Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:31:16 +00:00
Chris Lattner
2b8d30d080 Define a new BinOpRI8 class and use it to define the imm8 versions of and. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6 Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0 Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:56:46 +00:00
Jakob Stoklund Olesen
bf4699c561 Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE. 
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:54:39 +00:00
Jakob Stoklund Olesen
893ab5d701 Skip unused registers when verifying LiveIntervals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:54:35 +00:00
Jim Grosbach
fa7fb64fad remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7 First in a sequence of ARM/MC/*ELF* specific work. 
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:36:46 +00:00
Rafael Espindola
d8e0bfe07a Another case of 256 sections not being enough :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:28:19 +00:00
Owen Anderson
9875903799 Appease the clang self-host buildbot by providing a correct instantiation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:23:20 +00:00
Jim Grosbach
3c38f96af2 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7 Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed 
"lane" operand modifier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be 
pseudo instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:16:16 +00:00
Rafael Espindola
152c1061e0 Get binding and visibility info from the the alias, but Type from the symbol 
being aliased.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:02:29 +00:00
Owen Anderson
e9ef41a47d Hide analysis group registration behind a macro, just like pass registration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:02:27 +00:00
Devang Patel
d6747df5e0 Add support for DW_TAG_unspecified_parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:50:40 +00:00
Jim Grosbach
7cd2729d2a Add a 'pattern' arg to the ARM PseudoNeonI class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:36:55 +00:00
Michael J. Spencer
345ed9806a MC: Add missing forward in MCLoggingStreamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:36:47 +00:00
Bill Wendling
933f9bdb00 Revert "RequiresUnique" patch. This should be handled at a lower level. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:18:44 +00:00
Rafael Espindola
153666c038 If a symbol is global, reloc against it even if it is in a mergeable section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 19:27:21 +00:00
Nick Lewycky
9c220fc165 Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115802 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 18:11:50 +00:00
Jim Grosbach
4dea941c8d target operand flag values aren't a bitmask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:51:55 +00:00
Rafael Espindola
3223f19ff0 Make sure weak symbols are listed after the local ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:47:31 +00:00
Rafael Espindola
8cecf253e4 Correctly handle GOTPCREL relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:23:36 +00:00
Dan Gohman
0dadb15927 ComputeLinearIndex doesn't need its TLI argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:18:29 +00:00
Bill Wendling
c7a012e581 Change RequiresMerge to RequiresUnique. It's a better description of what this 
fix is trying to accomplish.

This code could still use some polishing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 07:03:52 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Bill Wendling
7f5124829f If the destination module all ready has a copy of the global coming from the 
source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.

The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.

<rdar://problem/8198537>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:16:30 +00:00
Chris Lattner
b2fc409827 enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad add a class for _REV nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:35:22 +00:00