4111 Commits

Author SHA1 Message Date
Timur Iskhodzhanov
6a7c74de33 Revert r226242 - Revert Revert Don't create new comdats in CodeGen
This breaks AddressSanitizer (ninja check-asan) on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226251 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-16 08:38:45 +00:00
Rafael Espindola
dfe88a08c7 Revert "Revert Don't create new comdats in CodeGen"
This reverts commit r226173, adding r226038 back.

No change in this commit, but clang was changed to also produce trivial comdats for
costructors, destructors and vtables when needed.

Original message:

Don't create new comdats in CodeGen.

This patch stops the implicit creation of comdats during codegen.

Clang now sets the comdat explicitly when it is required. With this patch clang and gcc
now produce the same result in pr19848.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226242 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-16 02:22:55 +00:00
Colin LeMahieu
c93be748d7 [Hexagon] Adding new-value store and bit reverse instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226224 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 23:10:29 +00:00
Colin LeMahieu
42fa763380 [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226194 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 19:28:32 +00:00
Colin LeMahieu
500b0d97a1 [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226184 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 18:16:00 +00:00
Joerg Sonnenberger
638077aa41 Support @PLT loads on 32bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226182 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 17:59:02 +00:00
Timur Iskhodzhanov
d048b3be70 Revert Don't create new comdats in CodeGen
It breaks AddressSanitizer on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226173 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 16:14:34 +00:00
Vladimir Medic
b6d562e480 Add disassembler tests for mips64r6 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 14:18:12 +00:00
Vladimir Medic
d83822e6d7 Add disassembler tests for mips32r6 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 14:11:38 +00:00
Vladimir Medic
e671c1cdb5 Add disassembler tests for mips64r2 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 14:06:34 +00:00
Vladimir Medic
dc67d7678a Add disassembler tests for mips64 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226151 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 08:50:20 +00:00
Hal Finkel
4572a0a0a2 [PowerPC] Add assembler support for mcrfs and friends
Fill out our support for the floating-point status and control register
instructions (mcrfs and friends). As it turns out, these are necessary for
compiling src/test/harness_fp.h in TBB for PowerPC.

Thanks to Raf Schietekat for reporting the issue!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226070 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 01:00:53 +00:00
Duncan P. N. Exon Smith
37ac8d3622 IR: Move MDLocation into place
This commit moves `MDLocation`, finishing off PR21433.  There's an
accompanying clang commit for frontend testcases.  I'll attach the
testcase upgrade script I used to PR21433 to help out-of-tree
frontends/backends.

This changes the schema for `DebugLoc` and `DILocation` from:

    !{i32 3, i32 7, !7, !8}

to:

    !MDLocation(line: 3, column: 7, scope: !7, inlinedAt: !8)

Note that empty fields (line/column: 0 and inlinedAt: null) don't get
printed by the assembly writer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226048 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 22:27:36 +00:00
Rafael Espindola
33f5127540 Don't create new comdats in CodeGen.
This patch stops the implicit creation of comdats during codegen.

Clang now sets the comdat explicitly when it is required. With this patch clang and gcc
now produce the same result in pr19848.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 20:55:48 +00:00
Rafael Espindola
a6b0d5a62e Add a test that would have found the issue with r225644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226035 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 20:24:46 +00:00
Rafael Espindola
8327f0bca1 Revert "Add r224985 back with two fixes."
This reverts commit r225644 while I debug a regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 19:07:23 +00:00
Vladimir Medic
81e68c9023 Add disassembler tests for mips32r2 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225980 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 11:35:22 +00:00
Jyoti Allur
fd06dd8efc Correct POP handling for v7m
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225972 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 10:48:16 +00:00
Vladimir Medic
8da9819ca7 Add disassembler tests for mips32r2 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225967 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 10:18:56 +00:00
Saleem Abdulrasool
1679d0d3c2 X86: validate 'int' instruction
The int instruction takes as an operand an 8-bit immediate value.  Validate that
the input is valid rather than silently truncating the value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225941 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 05:10:21 +00:00
Rafael Espindola
5512415ade Add r224985 back with two fixes.
One is that AArch64 has additional restrictions on when local relocations can
be used. We have to take those into consideration when deciding to put a L
symbol in the symbol table or not.

The other is that ld64 requires the relocations to cstring to use linker
visible symbols on AArch64.

Thanks to Michael Zolotukhin for testing this!

Remove doesSectionRequireSymbols.

In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225644 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-12 18:13:07 +00:00
Jozef Kolek
ad017096fc [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions
Differential Revision: http://reviews.llvm.org/D5271


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225627 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-12 12:03:34 +00:00
Saleem Abdulrasool
5e3c87ee1a ARM: add support for segment base relocations (SBREL)
This adds support for parsing and emitting the SBREL relocation variant for the
ARM target.  Handling this relocation variant is necessary for supporting the
full ARM ELF specification.  Addresses PR22128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-11 04:39:18 +00:00
Saleem Abdulrasool
9c4081dce4 tests: fix previous commit
The previous commit accidentally missed changes to the test output checking,
resulting in an errant failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225577 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-10 02:53:25 +00:00
Saleem Abdulrasool
e83fb8c282 test: merge ARM relocations test
There is a fair number of relocations that are part of the AAELF specification.
Simply merge the tests into a single test file, otherwise, we will end up with
far too many test files to test each relocation type.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225576 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-10 02:48:29 +00:00
Saleem Abdulrasool
cc597901e5 tests: convert a couple of ARM relocation tests to readobj
These tests are checking the relocation generation.  Use the readobj output as
it is much easier to follow when glancing over the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225575 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-10 02:48:25 +00:00
Saleem Abdulrasool
c2a1df7125 ARM: add support for R_ARM_ABS16
Add support for R_ARM_ABS16 relocation mapping.  Addresses PR22156.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225510 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 06:57:24 +00:00
Saleem Abdulrasool
466a7dea9b test: add additional test for SVN r225507
Add an additional test case to ensure that we generate the relocation even if
the thumb target is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 06:57:18 +00:00
Saleem Abdulrasool
ea4fe48b22 ARM: add support for R_ARM_ABS8 relocations
Add support for R_ARM_ABS8 relocation.  Addresses PR22126.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225507 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 05:59:12 +00:00
Craig Topper
367b67df3e [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225432 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 07:41:30 +00:00
Rafael Espindola
5061ecc615 Add a test that would have found the issue in r224935.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225385 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-07 21:10:25 +00:00
Colin LeMahieu
51817073b3 [Hexagon] Adding floating point classification and creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225374 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-07 20:28:57 +00:00
Colin LeMahieu
22ddfae848 [Hexagon] Adding encodings for v5 floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-07 20:24:09 +00:00
Colin LeMahieu
22efbc70a7 [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225371 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-07 20:07:28 +00:00
Colin LeMahieu
a602a7f199 [Hexagon] Adding compound jump encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225291 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 20:03:31 +00:00
Colin LeMahieu
3d1d6d9043 [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225283 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 19:03:20 +00:00
Colin LeMahieu
63d0449f11 [Hexagon] Adding encoding information for absolute address loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225279 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 18:38:26 +00:00
Tom Stellard
1f996fa36b R600/SI: Add a stub GCNTargetMachine
This is equivalent to the AMDGPUTargetMachine now, but it is the
starting point for separating R600 and GCN functionality into separate
targets.

It is recommened that users start using the gcn triple for GCN-based
GPUs, because using the r600 triple for these GPUs will be deprecated in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 18:00:21 +00:00
Colin LeMahieu
a24e012976 [Hexagon] Adding dealloc_return encoding and absolute address stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225267 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 16:15:15 +00:00
Craig Topper
f6145affbf [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 08:59:30 +00:00
Rafael Espindola
5165dfdf9a Add a testcase that would have found the problem in r225048.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225235 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 01:41:24 +00:00
Lang Hames
bce877c84c Revert r225048: It broke ObjC on AArch64.
I've filed http://llvm.org/PR22100 to track this issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225228 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 00:54:32 +00:00
Colin LeMahieu
e4f1dcdb83 [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225210 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 21:36:38 +00:00
Colin LeMahieu
ca96263b05 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:56:41 +00:00
Colin LeMahieu
27494b0633 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225199 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:35:54 +00:00
Colin LeMahieu
c8e734a561 [Hexagon] Adding V4 logic-logic instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:14:58 +00:00
Colin LeMahieu
e48ec2a918 [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225197 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 20:04:40 +00:00
Colin LeMahieu
9e989cf190 [Hexagon] Adding round reg/imm and bitsplit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 18:08:21 +00:00
Charlie Turner
6abfc44aab Parse Tag_compatibility correctly.
Tag_compatibility takes two arguments, but before this patch it would
erroneously accept just one, it now produces an error in that case.

Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:26:37 +00:00
Charlie Turner
b99b8ffb7f Emit the build attribute Tag_conformance.
Claim conformance to version 2.09 of the ARM ABI.

This build attribute must be emitted first amongst the build attributes when
written to an object file. This is to simplify conformance detection by
consumers.

Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 13:12:17 +00:00