5 Commits

Author	SHA1	Message	Date
Andrew Trick	922d314e8f	Instruction scheduling itinerary for Intel Atom. ... Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8	2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen	2e3e720d76	Fix some tests that depend on register allocation. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132602 91177308-0d34-0410-b5e6-96231b3b80d8	2011-06-03 22:45:21 +00:00
Jakob Stoklund Olesen	61396aebee	Fix a batch of x86 tests to be coalescer independent. ... Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130891 91177308-0d34-0410-b5e6-96231b3b80d8	2011-05-04 23:54:51 +00:00
Jakob Stoklund Olesen	b0e47cdf3d	Fix register-dependent X86 tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128867 91177308-0d34-0410-b5e6-96231b3b80d8	2011-04-05 00:32:44 +00:00
NAKAMURA Takumi	a2e0762fae	Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets. ... FIXME: Some cleanups would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8	2011-03-24 07:07:00 +00:00