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8909 Commits

Author SHA1 Message Date
Craig Topper
76f94fd361 Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 03:30:21 +00:00
Craig Topper
42ab0d75ab Remove 2 unused multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 02:02:45 +00:00
Craig Topper
5284f97632 Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171337 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 00:11:07 +00:00
Craig Topper
dd9ccdb050 Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171336 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-31 23:49:05 +00:00
Bill Wendling
94e94b3506 Use the predicate methods off of AttributeSet instead of Attribute. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171257 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-30 13:50:49 +00:00
Bill Wendling
8b62abdd7b Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-30 13:01:51 +00:00
Bill Wendling
831737d329 Remove the Function::getFnAttributes method in favor of using the AttributeSet 
directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-30 10:32:01 +00:00
Craig Topper
22d8f0d685 Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 18:18:20 +00:00
Craig Topper
6f57f39e4a Merge similar functionality using a nested switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171229 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 17:19:06 +00:00
Craig Topper
6d183e4007 Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 16:44:25 +00:00
Jakub Staszak
c20323a758 Simplify code, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171226 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 15:57:26 +00:00
Nadav Rotem
ae34b4280e CostModel: initial checkin for code that estimates the cost of special shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171180 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-28 08:19:03 +00:00
Nadav Rotem
40ef8b7548 wrap 80-col lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171179 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-28 07:28:43 +00:00
Nadav Rotem
0509db2738 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-28 05:45:24 +00:00
Nadav Rotem
587fb1dd30 Reverse the 'if' condition and reduce the indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171172 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 23:08:05 +00:00
Craig Topper
cccccabd07 Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171171 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 22:53:47 +00:00
Nadav Rotem
1a330af3b5 AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171170 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 22:47:16 +00:00
Craig Topper
d5fc507ff1 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171166 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 18:51:50 +00:00
Nadav Rotem
d6fb53adb1 On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 08:15:45 +00:00
Nadav Rotem
3c22a44400 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. 
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:45:10 +00:00
Craig Topper
068aec586d Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:16:08 +00:00
Craig Topper
d0f28c0958 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:34:54 +00:00
Craig Topper
87073aad8f Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:35:44 +00:00
Craig Topper
766cbae4b1 Mark the divide instructions as hasSideEffects=0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 03:01:18 +00:00
Craig Topper
0b9c5e268f Add hasSideEffects=0 to CMP*rr_REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:08:46 +00:00
Craig Topper
5e6a86c7f0 Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:01:33 +00:00
Craig Topper
e9fd6ad567 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52 Add hasSideEffects=0 to some atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:19:23 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7 Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:04:30 +00:00
Craig Topper
0a5ead92ff Merge still more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640 Merge more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:20:35 +00:00
Craig Topper
755841d9d7 Fix 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072 Fix class name in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:14:15 +00:00
Craig Topper
02082efaab Remove 'v' from mnemonic to fix asm matching failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 05:49:15 +00:00
Nadav Rotem
a05f7cbbde Reformat the docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:59:20 +00:00
Craig Topper
09a326d3f0 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d Merge an AVX/SSE 256-bit and 128-bit multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586 Mark VANDNPD/VANDNPDS as not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:48:10 +00:00
Craig Topper
174a3d3e63 Remove alignment from a bunch more VEX encoded operations in the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0 Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 01:47:12 +00:00
Craig Topper
0f77910e6f Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 00:35:47 +00:00
Benjamin Kramer
99f78061e0 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 13:09:08 +00:00
Benjamin Kramer
382ed78d3f X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. 
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 12:54:19 +00:00
Nadav Rotem
a4c8a32a9f VCVTSS2SD requires a strict alignment. Thanks Elena. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 03:29:18 +00:00
Nick Lewycky
71f30bffcf Quiet gcc's -Wparenthesis warning. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 19:58:45 +00:00