Commit Graph

5 Commits

Author SHA1 Message Date
Tim Northover
a9a94ce839 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 09:42:04 +00:00
Venkatraman Govindaraju
833687be0e [Sparc] Add fcmpe* instructions to Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 19:56:19 +00:00
Venkatraman Govindaraju
afad335cae [Sparc] Add support for parsing fcmp with %fcc registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
8c6a26194b [Sparc] Correct quad register list in the asm parser.
Add test cases to check parsing of v9 double registers and their aliased quad registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199974 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 05:24:01 +00:00
Venkatraman Govindaraju
fcb6800dd4 [Sparc] Add support for parsing floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-12 04:48:54 +00:00