6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00
Code Issues Projects Releases Wiki Activity
83,838 Commits 39 Branches 0 Tags
Commit Graph

22 Commits

Author SHA1 Message Date
Craig Topper
caea5e28b2 Add intrinsic forms for FMA instructions to opcode folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157917 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 07:46:16 +00:00
Craig Topper
529ce07c5f Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 07:26:46 +00:00
Craig Topper
57ae246a6a Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157895 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 01:40:43 +00:00
Craig Topper
60dda38008 Add neverHasSideEffects and mayLoad to FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157894 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 00:30:49 +00:00
Craig Topper
3a8172ad8d Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157804 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 06:07:48 +00:00
Craig Topper
d9567223e8 Tidy up. Remove trailing spaces and fix the worst of the 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157799 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 05:24:29 +00:00
Elena Demikhovsky
177cf1e1a3 Added FMA3 Intel instructions. 
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 09:20:20 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
193cf04f5b Mark scalar FMA4 instructions as ignoring the VEX.L bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147602 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-05 08:56:10 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9 Combine FMA4 SS/SD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b Combine FMA4 PS/PD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 01:49:53 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Craig Topper
19f18be449 Expose FMA3 instructions to the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:03:14 +00:00
Jan Sjödin
703420f50e Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 14:43:19 +00:00
Jan Sjödin
dd649e35e5 Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 22:09:42 +00:00
Bruno Cardoso Lopes
1b9b377975 This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-25 19:33:42 +00:00
Bruno Cardoso Lopes
6b7e9168a4 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:54:35 +00:00