6 Commits

Author	SHA1	Message	Date
Chris Lattner	919c032fa4	Modify the ppc backend to use two register classes for FP: F8RC and F4RC. ... These are used to represent float and double values, and the two regclasses contain the same physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8	2005-10-01 01:35:02 +00:00
Chris Lattner	043870dd85	Teach the code generator that rlwimi is commutable if the rotate amount ... is zero. This lets the register allocator elide some copies in some cases. This implements CodeGen/PowerPC/rlwimi-commute.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8	2005-09-09 18:17:41 +00:00
Misha Brukman	b5f662fa03	Remove trailing whitespace ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8	2005-04-21 23:30:14 +00:00
Nate Begeman	7af0248af4	Initial support for allocation condition registers ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8	2005-04-12 07:04:16 +00:00
Nate Begeman	cb90de37a7	Add ori reg, reg, 0 as a move instruction. This can be generated from ... loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8	2004-10-07 22:26:12 +00:00
Misha Brukman	f2ccb77ee9	PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8	2004-08-17 04:55:41 +00:00